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MEC1322 Datasheet(PDF) 340 Page - Microchip Technology |
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MEC1322 Datasheet(HTML) 340 Page - Microchip Technology |
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340 / 456 page ![]() MEC1322 DS00001719D-page 340 2014 - 2015 Microchip Technology Inc. 28.10.4 LED UPDATE STEPSIZE REGISTER This register has eight segment fields which provide the amount the current duty cycle is adjusted at the end of every PWM period. Segment field selection is decoded based on the segment index. The segment index equation utilized depends on the SYMMETRY bit in the LED Configuration Register Register) • In Symmetric Mode the Segment_Index[2:0] = Duty Cycle Bits[7:5]. • In Asymmetric Mode the Segment_Index[2:0] is the bit concatenation of following: Segment_Index[2] = (FALLING RAMP TIME in Figure 28-3, "Clipping Example") and Segment_Index[1:0] = Duty Cycle Bits[7:6]. This register may be written at any time. Values written into the register are held in an holding register, which is trans- ferred into the actual register at the end of a PWM period if the Enable Update bit in the LED Configuration register is set to 1. Reads of this register return the current contents and not the value of the holding register. In 8-bit mode, each 4-bit STEPSIZE field represents 16 possible duty cycle modifications, from 1 to 16 as the duty cycle is modified between 0 and 255: 15: Modify the duty cycle by 16 ... 1: Modify the duty cycle by 2 0: Modify the duty cycle by 1 In 7-bit mode, the least significant bit of the 4-bit field is ignored, so each field represents 8 possible duty cycle modifi- cations, from 1 to 8, as the duty cycle is modified between 0 and 127: 14, 15: Modify the duty cycle by 8 ... 2, 3: Modify the duty cycle by 2 0, 1: Modify the duty cycle by 1 In 6-bit mode, the two least significant bits of the 4-bit field is ignored, so each field represents 4 possible duty cycle modifications, from 1 to 4 as the duty cycle is modified between 0 and 63: 12, 13, 14, 15: Modify the duty cycle by 4 8, 9, 10, 11: Modify the duty cycle by 3 4, 5, 6, 7: Modify the duty cycle by 2 0, 1, 2, 3: Modify the duty cycle by 1 Offset 0Ch Bits Description Type Default Reset Event 31:28 UPDATE_STEP7 Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 111. R/W 0h VCC1_ RESET 27:24 UPDATE_STEP6 Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 110. R/W 0h VCC1_ RESET 23:20 UPDATE_STEP5 Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 101 R/W 0h VCC1_ RESET 19:16 UPDATE_STEP4 Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 100. R/W 0h VCC1_ RESET 15:12 UPDATE_STEP3 Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 011. R/W 0h VCC1_ RESET |
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