UPD1002 datasheet(24/46 Pages) MICROCHIP

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UPD1002

DS00001760B-page 24

 2014 Microchip Technology Inc.

3.3

Configuration Selection (CFG_SEL0/CFG_SEL1)

The UPD1002 provides a resistor/capacitor identification detection interface which is utilized to set various device con-

figuration parameters via the Configuration Select pins:

• CFG_SEL0

• CFG_SEL1

Each Configuration Select pin can discriminate a number of quantized RC constants. The judicious selection of RC val-

ues provides a low cost means for system element configuration identification. The Configuration Select pins measure

the charge/discharge time for the RC circuit connected to it (shown in Figure 3-1), providing the ability to differentiate

16 unique “bins” for each Configuration Select pin. The resistor and capacitor values for each Configuration Select bin

are defined in Table 3-2.

Note:

CFG_SEL0 and CFG_SEL1 bin definitions are identical.

FIGURE 3-1:

CFG_SEL0/CFG_SEL1 RESISTOR-CAPACITOR CIRCUIT CONNECTIONS

TABLE 3-2:

CFG_SELX PIN RESISTOR-CAPACITOR BIN ALLOCATION

Bin

Rx (+/-1%)

Cx (+/-5%)

12.70 k

None

22.70 k

470 pF

34.87 k

470 pF

48.66 k

470 pF

15.40 k

470 pF

62.70 k

4.7 nF

74.87 k

4.7 nF

88.66 k

4.7 nF

15.40 k

4.7 nF

2.70 k

47.0 nF

4.87 k

47.0 nF

8.66 k

47.0 nF

15.40 k

47.0 nF

2.70 k

470 nF

4.87 k

470 nF

8.66 k

470 nF

VDDIO

CFG_SEL0

Microchip

UPD1002

VDDIO

CFG_SEL1

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