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ISO721DR Datasheet(PDF) 21 Page - Texas Instruments |
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ISO721DR Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 37 page ![]() 0 75 50 25 100 125 150 175 200 0 50 100 150 200 CaseTemperature C o − V , =3.6V CC1 VCC2 V ,V =5.5V CC1 CC2 ISO721, ISO721M, ISO722, ISO722M www.ti.com SLLS629L – JANUARY 2006 – REVISED OCTOBER 2015 9.3.4 Package Insulation Characteristics PARAMETER DESCRIPTIONS / TEST CONDITIONS MIN TYP MAX UNIT D-8 4 L(101) Minimum air gap (clearance)(1) Shortest terminal-to-terminal distance through air mm DUB-8 6.1 D-8 4 Minimum external tracking Shortest terminal-to-terminal distance across the L(102) mm (creepage)(1) package surface DUB-8 6.8 Tracking resistance (comparative CTI DIN EN 60112 (VDE 0303-11); IEC 60112 400 V tracking index) DTI Distance through insulation Minimum internal gap (internal clearance) 0.008 mm Input to output, VIO = 500 V; all pins on each side of the 1012 Ω barrier tied together, creating a two-terminal device; TA = 25°C RIO Isolation resistance Input to output, VIO = 500 V, 1011 Ω 100°C ≤ TA< TA max. Barrier capacitance CIO VI = 0.4 sin (4 × 10 6πt) 1 pF Input-to-output (1) Creepage and clearance requirements are applied according to the specific equipment isolation standards of an application. Maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance. Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation Glossary in the Related Documentation section. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. 9.3.5 Safety Limiting Values Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply, and without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT θJA = 263°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C 100 IS Safety input, output, or supply current mA θJA = 263°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C 153 TS Maximum case temperature 150 °C The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The junction-to-air thermal resistance in the Thermal Information table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages and is conservative. Figure 16. θJC Thermal Derating Curve per VDE Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: ISO721 ISO721M ISO722 ISO722M |
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