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DRV8302

SLES267C – AUGUST 2011 – REVISED MARCH 2016

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Copyright © 2011–2016, Texas Instruments Incorporated

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Table 4. Buck Regulator External Components

NAME

PIN 1

PIN 2

RECOMMENDED

RT_CLK

GND (PowerPAD)

See Buck Converter

COMP

GND (PowerPAD)

See Buck Converter

COMP

GND (PowerPAD)

See Buck Converter

PH (Filtered)

VSENSE

See Buck Converter

VSENSE

GND (PowerPAD)

See Buck Converter

PWRGD

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≥ 10 kΩ

PH

PH (Filtered)

See Buck Converter

PH

GND (PowerPAD)

See Buck Converter

PH (Filtered)

GND (PowerPAD)

See Buck Converter

BST_BK

PH

See Buck Converter

PVDD2

GND (PowerPAD)

≥4.7 µF (20%) ceramic, rated for PVDD2

SS_TR

GND (PowerPAD)

See Buck Converter

7.3.4 Protection Features

The DRV8302 provides a broad range of protection features and fault condition reporting. The DRV8302 has

undervoltage and overtemperature protection for the IC. It also has overcurrent and undervoltage protection for

the MOSFET power stage. In fault shut down conditions all gate driver outputs is held low to ensure the external

MOSFETs are in a high impedance state.

7.3.4.1 Overcurrent Protection (OCP) and Reporting

be determined to trigger the overcurrent protection features when exceeded. The voltage threshold is

programmed through the OC_ADJ pin by applying an external reference voltage with a DAC or resistor divider

from DVDD. Overcurrent protection should be used as a protection scheme only; it is not intended as a precise

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MOSFET is enabled. The high-side sense is between the PVDD and SH_X pins. The low-side sense is between

the SH_X and SL_X pins. Ensuring a differential, low impedance connection to the external MOSFETs for these

There are two different overcurrent modes that can be set through the M_OC pin.

7.3.4.1.1

Current Limit Mode (M_OC = LOW)

In current limit mode the devices uses current limiting instead of device shutdown during an overcurrent event.

After the overcurrent event, the MOSFET in which the overcurrent was detected in will shut off until the next

PWM cycle. The overcurrent event will be reported through the nOCTW pin. The nOCTW pin will be held low for

a maximum 64 µs period (internal timer) or until the next PWM cycle. If another overcurrent event is triggered

from another MOSFET, during a previous overcurrent event, the reporting will continue for another 64 µs period

(internal timer will restart) or until both PWM signals cycle.

In current limit mode the device uses current limiting instead of device shutdown during an overcurrent event. In

this mode the device reports overcurrent events through the nOCTW pin. The nOCTW pin will be held low for a

maximum 64 µs period (internal timer) or until the next PWM cycle. If another overcurrent event is triggered from

another MOSFET, during a previous overcurrent event, the reporting will continue for another 64 µs period

(internal timer will restart) or until both PWM signals cycle.