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DRV8302 Datasheet(PDF) 7 Page - Texas Instruments |
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DRV8302 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 32 page  7 DRV8302 www.ti.com SLES267C – AUGUST 2011 – REVISED MARCH 2016 Product Folder Links: DRV8302 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated 6.5 Electrical Characteristics PVDD = 8 V to 60 V, TC = 25°C, unless specified under test condition PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT PINS: INH_X, INL_X, M_PWM, M_OC, GAIN, EN_GATE, DC_CAL VIH High input threshold 2 V VIL Low input threshold 0.8 V REN_GATE Internal pulldown resistor for EN_GATE 100 k Ω RINH_X Internal pulldown resistor for high side PWMs (INH_A, INH_B, and INH_C) EN_GATE high 100 k Ω RINH_X Internal pulldown resistor for low side PWMs (INL_A, INL_B, and INL_C) EN_GATE high 100 k Ω RM_PWM Internal pulldown resistor for M_PWM EN_GATE high 100 k Ω RM_OC Internal pulldown resistor for M_OC EN_GATE high 100 k Ω RDC_CAL Internal pulldown resistor for DC_CAL EN_GATE high 100 k Ω OUTPUT PINS: nFAULT AND nOCTW VOL Low output threshold IO = 2 mA 0.4 V VOH High output threshold External 47-k Ω pullup resistor connected to 3-5.5 V 2.4 V IOH Leakage current on open-drain pins When logic high (nFAULT and nOCTW) 1 µA GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C VGX_NORM Gate driver Vgs voltage PVDD = 8 V to 60 V 9.5 11.5 V Ioso1 Maximum source current setting 1, peak Vgs of FET equals to 2 V 1.7 A Iosi1 Maximum sink current setting 1, peak Vgs of FET equals to 8 V 2.3 A Rgate_off Gate output impedance during standby mode when EN_GATE low (pins GH_x, GL_x) 1.6 2.4 k Ω SUPPLY CURRENTS IPVDD1_STB PVDD1 supply current, standby EN_GATE is low. PVDD1 = 8 V. 20 50 µA IPVDD1_OP PVDD1 supply current, operating EN_GATE is high, no load on gate drive output, switching at 10 kHz, 100-nC gate charge 15 mA IPVDD1_HIZ PVDD1 Supply current, HiZ EN_GATE is high, gate not switching 2 5 11 mA INTERNAL REGULATOR VOLTAGE AVDD AVDD voltage 6 6.5 7 V DVDD DVDD voltage 3 3.3 3.6 V VOLTAGE PROTECTION VPVDD_UV Undervoltage protection limit, PVDD 6 V VGVDD_UV Undervoltage protection limit, GVDD 8 V VGVDD_OV Overvoltage protection limit, GVDD 16 V CURRENT PROTECTION, (VDS SENSING) VDS_OC Drain-source voltage protection limit 0.125 2.4 V Toc OC sensing response time 1.5 µs TOC_PULSE OCTW pin reporting pulse stretch length for OC event 64 µs |
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