TPIC2040 datasheet(21/57 Pages) TI1

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Hi -Z

SIMO

SCLK

SOMI

SSZ

D11

D10

Hi -Z

SIMO

SCLK

SOMI

SSZ

TPIC2040

www.ti.com

SLIS172 – DECEMBER 2015

8.5 Programming

8.5.1 Serial Port Functional Description

The serial communication of TPIC2040 is based on a SPI communications protocol. TPIC2040 is put on the

slave side.

All 16-bit transmission data is effective in SSZ = L period.

The bit stream sent through SIMO from a master (DSP) is latched to an internal shift register by the rising edge

of SCLK. All the data is transmitted in a total of 16-bit format of a command and data. A format has two types of

data, 8 bits and 12 bits length. In order to access specific registers, an address and R/W flag are specified as a

command part. In addition, 12-bit data do not have R/W flag in the packet because DAC register

　(= 12-bit data

form) are Write only. A transfer packet, command and data, is transmitted sequentially from MSB to LSB. A

packet is distinguished in MSB 2 bits of command. In the case of 11, it handles a packet for control register

access, and the other processed as a packet for a DAC data setting.

There are the following four kinds of serial-data communication packets.

1. Write 12 bits DAC data (MSB two bit

≠ 11)

2. Write 8 bits control register (MSB two bit = 11)

3. Read 8 bits control register (MSB two bit = 11)

4. Write 12 bits Focus DAC data

＋Read 8 bits status register at the same time (MSB two bit ≠ 11)

8.5.2 Write Operation

For write operation, DSP transmits 16 bit (command + address + data) data a bit every in an order from MSB.

Only the 16-bit data which means 16 SCLK sent from the master during SSZ = L becomes effective. If more than

17 or less than 15 SCLK pulses are received during the time that SSZ is low, the whole packet will be ignored.

For all valid write operations, the data of the shift register is latched into its designated internal register at rising

edge of 16th SCLK. All internal register bits, except indicated otherwise, are reset to their default states upon

power-on-reset.

Figure 15. Write 12-Bits DAC Data

Figure 16. Write 8-Bits Control Register

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