Data Sheet TLE 6225 G

V2.1

Page

26.Aug. 2002

5

Functional Description

The TLE 6225 G is a quad channel low-side switch with four power DMOS stages. The power

voltage by zenerclamp.

The diagnostic logic recognises a fault condition which is indicated by a fault flag.

Circuit Description

Output Stage Control

Each output is independently controlled by an input pin and a common enable line, which en-

ables/disables all four outputs. The parallel inputs are high or low active depending on the

PRG pin. If the parallel input pins are not connected (independent of high or low activity) it is

guaranteed that the outputs 1 to 4 are switched OFF. ENA - and PRG - pin itself are internally

pulled down when they are not connected.

ENA - Enable pin.

ENA = High:

Active mode. Channels are enabled

ENA = Low (GND): Sleep mode. Channels are switched off. Less than

1 µA current consumption.

PRG - Program pin.

PRG = High:

Parallel inputs Channel 1 to 4 are high active

PRG = Low (GND): Parallel inputs Channel 1 to 4 are low active.

Power Transistors

Each of the four output stages has its own zenerclamp. This causes a voltage limitation at the

power transistors when inductive loads are switched off. The outputs are provided with a cur-

rent limitation set to a minimum of 500 mA.

Each output is protected by embedded protection functions

short to supply, the current is internally limited. If this operation leads to an overtemperature

condition, a second protection level (about 170 °C) will turn the effected output into a PWM-

mode (selective thermal shutdown with restart) to prevent critical chip temperatures. The tem-

perature hysteresis is typically 10K.

Diagnostic

PRG.

FAULT - pin.

FAULT

= High

no fault @ PRG = High

FAULT

= Low

no fault @ PRG = Low

nently