ATMEGA323L datasheet(89/247 Pages) ATMEL

89 / 247 page

ATmega323(L)

1457G–AVR–09/03

The decision of the logic level of the received bit is taken by doing a majority voting of

the logic value to the three samples in the center of the received bit. The center samples

are emphasized on the figure by having the sample number inside boxes. The majority

voting process is done as follows: If two or all three samples have high levels, the

received bit is registered to be a logic 1. If two or all three samples have low levels, the

received bit is registered to be a logic 0. This majority voting process act as a low pass

filter for the incoming signal on the RxD pin. The recovery process is then repeated until

a complete frame is received. Including the first stop bit. Note that the Receiver only

uses the first stop bit of a frame.

Figure 51 shows the sampling of the stop bit and the earliest possible beginning of the

start bit of the next frame.

Figure 51. Stop Bit Sampling and Next Start Bit Sampling

The same majority voting is done to the stop bit as done for the other bits in the frame. If

the stop bit is registered to have a logic 0 value, the Frame Error (FE) Flag will be set.

A new high to low transition indicating the start bit of a new frame can come right after

the last of the bits used for majority voting. For normal speed mode, the first low level

sample can be at point marked (A) in Figure 51. For double speed mode the first low

level must be delayed to (B). (C) marks a stop bit of full length. The early start bit detec-

tion influences the operational range of the Receiver.

Asynchronous Operational

Range

The operational range of the Receiver is dependent of the mismatch between the

received bit rate and the internally generated baud rate. If the Transmitter is sending

frames at too fast or too slow bit rates, or the internally generated baud rate of the

Receiver does not have exact base frequency, the Receiver will not be able to synchro-

nize the frames to the start bit.

The following equations can be used to calculate the ratio of the incoming data rate and

internal Receiver baud rate.

Sum of character size and parity size (D = 5 to 10 bit).

Samples per bit. S = 16 for Normal Speed mode and

S = 8 for Double Speed mode.

First sample number used for majority voting. S

F = 8 for Normal Speed and

F = 4 for Double Speed mode.

Middle sample number used for majority voting. S

M = 9 for Normal Speed and

M = 5 for Double Speed mode.

0/1

STOP 1

123

0/1

RxD

Sample

(U2X = 0)

Sample

(U2X = 1)

(A)

(B)

(C)

slow

()S

–

⋅

-------------------------------------------

fast

()S

()SS

-----------------------------------

ATMEGA323L Datasheet(PDF) 89 Page - ATMEL Corporation

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