ATMEGA323-8AI datasheet(98/247 Pages) ATMEL

98 / 247 page

ATmega323(L)

1457G–AVR–09/03

• Bit 2:1 – UCSZ1:0: Character Size

The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits

(character size) in a frame the Receiver and Transmitter uses.

• Bit 0 – UCPOL: Clock Polarity

This bit is used for synchronous mode only. Set this bit to zero when asynchronous

mode is used. The UCPOL bit sets the relationship between data output change and

data input sample, and the synchronous clock (XCK).

USART Baud Rate Registers –

UBRRL and UBRRHs

The UBRRH Register shares the same I/O location as the UCSRC Register. See the

“Accessing UBRRH/UCSRC Registers” on page 92 section which describes how to

access this register.

• Bit 15 – URSEL: Register Select

This bit selects between accessing the UBRRH or the UCSRC Register. It is read as

zero when reading UBRRH. The URSEL must be zero when writing the UBRRH.

• Bit 14:12 – Reserved Bits

These bits are reserved for future use. For compatibility with future devices, these bit

must be set to zero when UBRRH is written.

Table 35. Character Size

UCSZ2

UCSZ1

UCSZ0

Character Size

5-bit

6-bit

7-bit

8-bit

100

Reserved

101

Reserved

110

Reserved

9-bit

UCPOL

Transmitted Data Changed (Output

of TxD Pin)

Received Data Sampled (Input on

RxD Pin)

Falling XCK Edge

Rising XCK Edge

Falling XCK Edge

Bit

151413121110

$20 ($40)

URSEL

–

UBRR[11:8]

UBRRH

$09 ($29)

UBRR[7:0]

UBRRL

76543210

Read/Write

R/W

Initial Value

00000000

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