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ATMEGA323-8AI Datasheet(PDF) 49 Page - ATMEL Corporation |
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ATMEGA323-8AI Datasheet(HTML) 49 Page - ATMEL Corporation |
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49 / 247 page  49 ATmega323(L) 1457G–AVR–09/03 The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the CK Oscillator clock for Timer/Counter0 and PCK2 for Timer/Counter2. If the external pin modes are used for Timer/Counter0, transitions on PB0(T0) will clock the counter even if the pin is configured as an output. This feature can give the user SW control of the counting. Timer Counter0 – TCNT0 Timer/Counter2 – TCNT2 These 8-bit registers contain the value of the Timer/Counters. Both Timer/Counters is realized as up or up/down (in PWM mode) counters with read and write access. If the Timer/Counter is written to and a clock source is selected, it con- tinues counting in the timer clock cycle following the write operation. Timer/Counter0 Output Compare Register – OCR0 Timer/Counter2 Output Compare Register – OCR2 The Output Compare Registers are 8-bit read/write registers. The Timer/Counter Output Compare Registers contains the data to be continuously com pared with the Timer/Counter. Actions on compare matches are specified in TCCR0 and TCCR2. A software write to the Timer/Counter Register blocks compare matches in the next Timer/Counter clock cycle. This prevents immediate interrupts when initializing the Timer/Counter. A Compare Match will set the Compare Interrupt Flag in the CPU clock cycle following the compare event. Timer/Counter 0 and 2 in PWM Mode When PWM mode is selected, the Timer/Counter either wraps (overflows) when it reaches $FF or it acts as an up/down counter. If the up/down mode is selected, the Timer/Counter and the Output Compare Registers – OCR0 or OCR2 form an 8-bit, free running, glitch-free and phase correct PWM with outputs on the PB3(OC0/PWM0) or PD7(OC2/PWM2) pin. If the overflow mode is selected, the Timer/Counter and the Output Compare Registers – OCR0 or OCR2 form an 8-bit, free running and glitch-free PWM, operating with twice the speed of the up/down counting mode. Bit 76543210 $32 ($52) MSB LSB TCNT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 00000000 Bit 76543210 $24 ($44) MSB LSB TCNT2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 00000000 Bit 76543210 $3C ($5C) MSB LSB OCR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 00000000 Bit 76543210 $23 ($43) MSB LSB OCR2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 00000000 |
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