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FPD87346 Datasheet(PDF) 2 Page - Texas Instruments |
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FPD87346 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 5 page ![]() Data Path & Timing Ref. 8-6 Bit Translator RxIN[3]± RxIN[2]± RxIN[1]± RxIN[0]± RxCLK± RSDS[2:0] RSR[2:0]P/N RSG[2:0]P/N RSB[2:0]P/N STH RSTZ RPI Column & Row Driver Control RSCKP/N Vertical & Horizontal Timing Generation OBSOLETE FPD87346 SNOSA51A – MAY 2004 – REVISED APRIL 2013 www.ti.com Block Diagram Figure 2. Block Diagram Functional Description FPD-LINK RECEIVER The LVDS based FPD-Link Receiver inputs video data and control timing through 4-LVDS channels plus clock to provide 24-bit color or 3-LVDS channels can be used for 18-bit color. The video data is converted to a parallel data stream and routed to the 8-6 bit translator. SPREAD SPECTRUM SUPPORT The FPD-Link receiver supports graphics controllers with Spread Spectrum interfaces for reducing EMI. The Spread Spectrum methods supported are Center and Down Spread. A maximum of 2% total is supported at a frequency modulation of 100kHz maximum. 8-6 BIT TRANSLATOR 8-bit data is reduced to a 6-bit data path via a time multiplexed dithering technique or simple truncation of the LSBs. This function is enabled via the input control pins. DATAPATH BLOCK AND RSDS TRANSMITTER 6(8)-bit video data (RGB) is input to the Datapath Block supports up to an 85 MHz pixel rate. The data is delayed to align the Column Driver Start Pulse (STH) with the Column Driver data. The data bus (RSR[2:0]P/N, RSG[2:0]P/N, RSB[2:0]P/N) outputs at a 170 MHz rate on 9 differential output channels. The clock is output on the RSCKP/N differential pair. The RSDS Column Drivers latch data on both positive and negative edges of the clock. The RSDS output setup/hold timings are also adjustable through the RSDS[2:0] input pins. TIMING CONTROL FUNCTION The Timing Control function generates control to Column Drivers, Row Drivers, and power supply. The GPOs (General Purpose Outputs) provide for CD latch pulse, REV, and Row Driver control generation. The General Purpose Outputs allow the user to generate control anywhere within the frame data. Standard Row Driver interface or Custom Row Driver interfaces can be implemented with the GPOs (General Purpose Outputs). RSDS OUTPUT VOLTAGE CONTROL The RSDS output voltage swing is controlled through an external load resistor connected to the RPI pin. The RSDS output signal levels can be adjusted to suit the particular application. This is dependent on overall LCD module design characteristics such as trace impedance, termination, etc. The RSDS output voltage is inversely related to the RPI value. Lower RPI values will increase the RSDS output voltage swing and consequently overall power consumption will also increase. 2 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: FPD87346 |
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