OBSOLETE

FPD87346

www.ti.com

SNOSA51A – MAY 2004 – REVISED APRIL 2013

FPD87346 Low EMI, Low Dynamic Power (SVGA) XGA/WXGA TFT-LCD Timing Controller

with Reduced Swing Differential Signaling (RSDS™) Outputs

Check for Samples: FPD87346

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FEATURES

DESCRIPTION

The FPD87346 is a timing controller that combines

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•

Reduced Swing Differential Signalling

an LVDS single pixel input interface with TI's

(RSDS™) Digital Bus Reduces Dynamic

Reduced

Swing

Differential

Signaling

(RSDS™)

Power, EMI and Bus Width from the Timing

output driver interface for (SVGA) XGA and Wide

Controller

XGA resolutions. It resides on the TFT-LCD panel

•

LVDS Single Pixel Input Interface System

and provides the data buffering and control signal

generation for (SVGA) XGA, and Wide XGA graphic

•

Input Clock Range from 40 MHz to 85 MHz

modes. The RSDS™ path to the column driver

•

Drives RSDS™ Column Drivers at 170 Mb/s

contributes

toward

lowering

radiated

EMI

and

with an 85 MHz Clock (Max.)

reducing system dynamic power consumption.

•

Virtual 8 Bit Color Depth in FRC/Dithering

This single RSDS™ bus conveys the 8-bit color data

Mode

for (SVGA) XGA, and Wide XGA panels at 170 Mb/s

•

Single Narrow 9-Bit Differential Source Driver

when using VESA 60 Hz standard timing.

Bus Minimizes Width of Source PCB

•

Ability to Drive (SVGA) XGA and Wide XGA

TFT-LCD Systems

•

Failure Detect Function in DE Mode

•

CMOS Circuitry Operates from a 3.0V–3.6V

Supply

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

System Diagram

Figure 1. Block Diagram of the LCD Module

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PRODUCTION DATA information is current as of publication date.

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Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

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