5

PIN IDENTIFICATION and DESCRIPTION

Logic Pins

Pin Name

Direction

Pin

Number

Description

MODE

I

M11

Mode select

0: Banks 0-3 are selected with BANK[1:0] and bank 0-3 chip selects are selected

with ASEL[2:0].

1: Banks 0-1 are selected with BANK[0] and bank 0-1 chip selects are selected

with BSEL[2:0]. Banks 2-3 are selected with BANK[1] and bank 2-3 chip

selects are selected with ASEL[2:0].

RAMS

I

M10

Enables banks 0-3 in mode 0 and banks 2-3 in mode 1.

ROMS

I

N10

Enables banks 0-1 in mode 1. Don’t care in mode 0.

ASEL[0]

I

P9

Bit 0 to select chip selects for banks 0-3 in mode 0 and for banks 2-3 in mode 1.

ASEL[1]

I

P10

Bit 1 to select chip selects for banks 0-3 in mode 0 and for banks 2-3 in mode 1.

ASEL[2]

I

R10

Bit 2 to select chip selects for banks 0-3 in mode 0 and for banks 2-3 in mode 1.

BSEL[0]

I

U7

Bit 0 to select chip selects for banks 0-1 in mode 1.

BSEL[1]

I

N9

Bit 1 to select chip selects for banks 0-1 in mode 1.

BSEL[2]

I

M9

Bit 2 to select chip selects for banks 0-1 in mode 1.

BANK[0]

I

U6

Bit 0 to select banks 0-3 in mode 0 and banks 0-1 in mode 1.

BANK[1]

I

U8

Bit 1 to select banks 0-3 in mode 0 and banks 2-3 in mode 1.

CS0[0]

O

W5

Bank 0 chip select 0. Asserted when xSEL[2:0] = 000b.

CS0[1]

O

Y6

Bank 0 chip select 1. Asserted when xSEL[2:0] = 001b.

CS0[2]

O

V9

Bank 0 chip select 2. Asserted when xSEL[2:0] = 010b.

CS0[3]

O

Y4

Bank 0 chip select 3. Asserted when xSEL[2:0] = 011b.

CS0[4]

O

W9

Bank 0 chip select 4. Asserted when xSEL[2:0] = 100b.

CS0[5]

O

P8

Bank 0 chip select 5. Asserted when xSEL[2:0] = 101b.

CS0[6]

O

R9

Bank 0 chip select 6. Asserted when xSEL[2:0] = 110b.

CS0[7]

O

U10

Bank 0 chip select 7. Asserted when xSEL[2:0] = 111b.

CS1[0]

O

W6

Bank 0 chip select 0. Asserted when xSEL[2:0] = 000b.

CS1[1]

O

V7

Bank 1 chip select 1. Asserted when xSEL[2:0] = 001b.

CS1[2]

O

W8

Bank 1 chip select 2. Asserted when xSEL[2:0] = 010b.

CS1[3]

O

W4

Bank 1 chip select 3. Asserted when xSEL[2:0] = 011b.

CS1[4]

O

Y10

Bank 1 chip select 4. Asserted when xSEL[2:0] = 100b.

CS1[5]

O

R7

Bank 1 chip select 5. Asserted when xSEL[2:0] = 101b.

36-00-03-001

Aeroflex Microelectronics Solutions - HiRel