UT64BS1X433CPC datasheet(6/20 Pages) AEROFLEX

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CS1[6]

Bank 1 chip select 6. Asserted when xSEL[2:0] = 110b.

CS1[7]

V10

Bank 1 chip select 7. Asserted when xSEL[2:0] = 111b.

CS2[0]

Bank 2 chip select 0. Asserted when xSEL[2:0] = 000b.

CS2[1]

Bank 2 chip select 1. Asserted when xSEL[2:0] = 001b.

CS2[2]

Bank 2 chip select 2. Asserted when xSEL[2:0] = 010b.

CS2[3]

Bank 2 chip select 3. Asserted when xSEL[2:0] = 011b.

CS2[4]

Bank 2 chip select 4. Asserted when xSEL[2:0] = 100b.

CS2[5]

Bank 2 chip select 5. Asserted when xSEL[2:0] = 101b.

CS2[6]

Bank 2 chip select 6. Asserted when xSEL[2:0] = 110b.

CS2[7]

Bank 2 chip select 7. Asserted when xSEL[2:0] = 111b.

CS3[0]

Bank 3 chip select 0. Asserted when xSEL[2:0] = 000b.

CS3[1]

Bank 3 chip select 1. Asserted when xSEL[2:0] = 001b.

CS3[2]

Bank 3 chip select 2. Asserted when xSEL[2:0] = 010b.

CS3[3]

W10

Bank 3 chip select 3. Asserted when xSEL[2:0] = 011b.

CS3[4]

Bank 3 chip select 4. Asserted when xSEL[2:0] = 100b.

CS3[5]

Bank 3 chip select 5. Asserted when xSEL[2:0] = 101b.

CS3[6]

T10

Bank 3 chip select 6. Asserted when xSEL[2:0] = 110b.

CS3[7]

Bank 3 chip select 7. Asserted when xSEL[2:0] = 111b.

XIN[0]

T14

Buffered input X[0]

XIN[1]

Buffered input X[1]

YIN[0]

N11

Buffered input Y[0]

YIN[1]

Buffered input Y[1]

XOUT[0]

U14

Bit 0 of buffered output X

XOUT[1]

T15

Bit 1 of buffered output X

XOUT[2]

P12

Bit 2 of buffered output X

XOUT[3]

U13

Bit 3 of buffered output X

YOUT[0]

N12

Bit 0 of buffered output Y

YOUT[1]

P11

Bit 1 of buffered output Y

YOUT[2]

M12

Bit 2 of buffered output Y

YOUT[3]

R11

Bit 3 of buffered output Y

Pin Name

Direction

Number

Description

36-00-03-001

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