Silicon Image, Inc.

SiI 150A

SiI/DS-0006-C

Revision C

3

Subject to Change without Notice

AC Specifications

Under normal operating conditions unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

T

CIP

IDCK Period, 1 Pixel/Clock

8.93

50

ns

F

CIP

IDCK Frequency, 1 Pixel/Clock

20

112

MHz

T

CIP

IDCK Period, 2 Pixels/Clock

17.8

100

ns

F

CIP

IDCK Frequency, 2 Pixels/Clock

10

56

MHz

T

CIH

IDCK High Time at 112MHz

4

ns

T

CIL

IDCK Low Time at 112MHz

4

ns

T

IJIT

Worst Case IDCK Clock Jitter

2,3

2ns

T

SIDF

Data, DE, VSYNC, HSYNC, and CTL[3:1]

Setup Time to IDCK falling edge

EDGE = 0

1

ns

T

HIDF

Data, DE, VSYNC, HSYNC, and CTL[3:1]

Hold Time from IDCK falling edge

EDGE = 0

3

ns

T

SIDR

Data, DE, VSYNC, HSYNC, and CTL[3:1]

Setup Time to IDCK rising edge

EDGE = 1

1

ns

T

HIDR

Data, DE, VSYNC, HSYNC, and CTL[3:1]

Hold Time from IDCK rising edge

EDGE = 1

3

ns

T

DDF

VSYNC, HSYNC, and CTL[3:1] Delay from DE falling edge

1

T

CIP

ns

T

DDR

VSYNC, HSYNC, and CTL[3:1] Delay to DE rising edge

1

T

CIP

ns

T

HDE

DE high time

1

8191T

CIP

ns

T

LDE

DE low time

1

128T

CIP

ns

S

LHT

Small Swing Low-to-High

Transition Time

C

R

R

0.25

0.3

0.35

ns

S

HLT

Small Swing High-to-Low

Transition Time

C

R

R

0.25

0.3

0.35

ns

Notes:

1

Guaranteed by design.

2

Jitter can be estimated by 1) triggering a digital scope at the rising of input clock and 2) measuring the peak to peak time spread

of the rising edge of the input clock 1

µs after the trigger.

3

Actual jitter tolerance may be higher depending on the frequency of the jitter.

Timing Diagrams

T

CIH

T

CIL

T

CIP

2.0 V

0.8 V

0.8 V

2.0 V

2.0 V

Figure 1. Clock Cycle/High/Low Times

Figure 2. Small Swing Transition Times

S

LHT

20% V

OD

80% V

OD

S

HLT