Silicon Image, Inc.

SiI 150A

SiI/DS-0006-C

Revision C

4

Subject to Change without Notice

Input Timing

Figure 3. Input Data Setup/Hold Times to IDCK

Figure 4. VSYNC, HSYNC, and CTL[3:1] Delay Times from DE

DE

T

LDE

T

HDE

0.8 V

2.0 V

0.8 V

2.0 V

Figure 5. DE High/Low Times

Input Pin Description

Pin Name

Pin #

Type

Description

DIE23-

DIE0

See SiI

150A Pin

Diagram

In

Even Input Data[23:0] corresponds to 24-bit pixel data for 1-pixel/clock input mode or to the first 24-bit

pixel data for 2-pixels/clock mode.

Input data is synchronized to input data clock (IDCK).

Data can be latched on the rising or the falling edge of IDCK depending on whether EDGE is high or low,

respectively.

Refer to the TFT and DSTN Signal Mapping application notes (Si

I-AN-0008-A and SiI-AN-0007-A,

respectively) which tabulate the relationship between the input data to the transmitter and output data from

the receiver.

DIO23 –

DIO0

See SiI

150A Pin

Diagram

In

Input Odd Data[23:0] corresponds to the second 24-bit pixel data for 2-pixels/clock mode.

In 1-pixel/clock mode, these inputs are a don’t care. Recommendation is to tie them low for lower power

consumption.

Input data is synchronized to input data clock (IDCK).

Data can be latched on the rising or the falling edge of IDCK depending on whether EDGE is high or low,

respectively.

Refer to the TFT and DSTN Signal Mapping application notes (Si

I-AN-0008-A and SiI-AN-0007-A,

respectively) which tabulate the relationship between the input data to the transmitter and output data from

the receiver.

IDCK

80

In

Input Data Clock. Input data and control signals can be valid either on the falling or the rising edge of

IDCK as selected by the EDGE pin.

DE

78

In

Input Data Enable. This signal qualifies the active data area. DE is always required by the transmitter and

must be high during active display time and low during blanking time.

HSYNC

VSYNC

76

77

In

In

Horizontal Sync input control signal.

Vertical Sync input control signal.

CTL1

CTL2

CTL3

84

83

82

In

In

In

General input control signal 1.

General input control signal 2.

General input control signal 3.

D[23:0], DE,

HSYNC,VSYNC,

CTL[3:1]

IDCK+/IDCK-

T

SIDF

T

HIDF

T

SIDR

T

HIDR

50 %

50 %

50 %

50 %

T

DDR

T

DDF

DE

VSYNC, HSYNC,

CTL[3:1]

0.8 V

0.8 V

0.8 V

0.8 V

DE

VSYNC, HSYNC,

CTL[3:1]