SL1640

Conditions

Signal: 70mVrms, 1.75MHz

Carrier: 100mV rms, 28.25MHz

Output: 30MHz

Signal: 70mVrms, 30MHz

Carrier: 100mV rms, 28.25MHz

Output: 1.75MHz

Signal 1: 42.5mVrms, 1.75MHz

Signal 2: 42.5mV rms, 2MHz

Carrier: 100mV rms, 28.25MHz

Output: 29.75MHz

ELECTRICAL CHARACTERISTICS

These characteristics are guaranteed over the following conditions (unless otherwise stated)

Ambient temperature: 22

°C ± 2°C

Value

Circuit

SL1640

SL1640

SL1640

SL1640

SL1640

SL1640

SL1640

Characteristics

Supply current

Conversion gain

Noise figure

Carrier input impedance

Signal input impedance

Maximum input voltage

Signal leak

Signal leak

Intermodulation products

-3

12

0

10

1

500

210

-30

-18

-45

17

+3

Units

Min.

Typ.

Max.

mA

dB

dB

K

Ω

Ω

K

Ω

mV rms

dB

dB

dB

APPLICATION NOTES

The SL1640 requires input and output coupling capacitors

which normally should be chosen to present a low reactance

compared with the input and output impedances (see

Electrical Characteristics). However, for minimum carrier leak

at high frequencies the signal input should be driven from a low

impedance source, in which case the signal input capacitor

reactance should be comparable with the source impedance.

Pin 2 must be decoupled to earth via a capacitor which

presents the lowest possible impedance at both carrier and

signal frequencies. The presence of these frequencies at Pin

2 would give rise to poor rejection figures and to distortion

There are two outputs from the SL1640: one is a voltage

source of output impedance 350 ohms and 8pF and the other

is the emitter of an emitter follower connected to the first output.

The output on pin 6 requires a discrete load resistor of not less

than 1500 ohms to ground. The emitter follower output should

not be used to drive capacitive loads as emitter followers act

as detectors under such circumstances with resultant

distortion and harmonic generation.

Frequency shaping

components may be connected to the voltage output and the

shaped signal taken from the emitter follower.

Signal and carrier leak may be reduced by altering the bias

on the carrier and signal input pins, as shown in Fig.3. With

carrier but no signal R1 is adjusted for minimum carrier leak

A similar network is connected to the carrier input and with

signal and carrier present, signal leak is minimised by means

of R2.

Fig.3 Signal and carrier leak adjustment