LP8556 datasheet(31/63 Pages) TI1

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'0'

Slave Address

(7 bits)

Control Register Add.

(8 bits)

Data- Data

(8 bits)

R/W

Data transfered, byte

Ack/NAck

Slave Address

(7 bits)

'1' A

R/W

Direction of the transfer

will change at this point

From Master to Slave

From Slave to Master

A - ACKNOWLEDGE (SDA Low)

S - START CONDITION

P - STOP CONDITION

Sr - REPEATED START CONDITION

NA - ACKNOWLEDGE (SDA High)

'0'

Slave Address

(7 bits)

Control Register Add.

(8 bits)

R/W

From Master to Slave

From Slave to Master

A - ACKNOWLEDGE (SDA Low)

S - START CONDITION

P - STOP CONDITION

Data transfered,

byte + Ack

LP8556

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SNVS871I – JULY 2012 – REVISED MARCH 2016

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Programming (continued)

Table 8. Data Read and Write Cycles

ADDRESS MODE

Data Read

<Slave Address><r/w = 0>[Ack]

<Register Addr.>[Ack]

<Slave Address><r/w = 1>[Ack]

[Register Data]<Ack or NAck>

… additional reads from subsequent register address possible

Data Write

<Slave Address><r/w=’0’>[Ack]

<Register Addr.>[Ack]

<Register Data>[Ack]

… additional writes to subsequent register address possible

<>Data from master [ ] Data from slave

8.5.1.8 Register Read and Write Detail

Figure 17. Register Write Format

Figure 18. Register Read Format

LP8556 Datasheet(PDF) 31 Page - Texas Instruments

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