ADG5404F datasheet(29/30 Pages) AD

29 / 30 page

Data Sheet

ADG5404F

Rev. B | Page 29 of 30

For systems sensitive during a start-up sequence, the active low

operation of the flag allows the system to ensure that the

ADG5404F is powered on and that all input voltages are within

the normal operating range before initiating operation.

The FF pin is a weak pull-up, which allows the signals to

combine into a single interrupt for larger modules that contain

multiple devices.

The recovery time, tDIGREC, can be decreased from a typical 60 µs

to 600 ns by using a 1 kΩ pull-up resistor.

The specific fault digital output, SF can be used to decode

which inputs are experiencing a fault condition. The SF pin

reduces to below 0.8 V when a fault condition is detected on a

specific pin, depending on the state of F0 and F1 (see Table 9).

LARGE VOLTAGE, HIGH FREQUENCY SIGNALS

Figure 30 shows the voltage range and frequencies that the

ADG5404F can reliably convey. For signals extending across the

full signal range from VSS to VDD, keep the frequency below 3 MHz.

If the required frequency is greater than 3 MHz, decrease the signal

range appropriately to ensure signal integrity.

ADG5404F Datasheet(PDF) 29 Page - Analog Devices