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SP6121 Datasheet(PDF) 14 Page - Sipex Corporation

Part # SP6121
Description  Low Voltage, Synchronous Step Down PWM Controller Ideal for 2A to 10A, Small Footprint, DC-DC Power Converters
PDF  16 Pages
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Manufacturer  SIPEX [Sipex Corporation]
Direct Link  http://www.sipex.com
Logo SIPEX - Sipex Corporation

SP6121 Datasheet(HTML) 14 Page - Sipex Corporation

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Date: 5/25/04
SP6121 Low Voltage, Synchronous Step Down PWM Controller
© Copyright 2004 Sipex Corporation
14
PCB layout plays a critical role in proper func-
tion of the converters and EMI control. In switch
mode power supplies, loops carrying high di/dt
give rise to EMI and ground bounces. The goal
of layout optimization is to identify these loops
and minimize them. It is also crucial on how to
connect the controller ground such that its op-
eration is not affected by noise. The following
guideline should be followed to ensure proper
operation.
1. A ground plane is recommended for minimiz-
ing noises, copper losses and maximizing heat
dissipation.
2. Begin the layout by placing the power compo-
nents first. Orient the power circuitry to achieve
a clean power flow path. If possible make all the
connections on one side of the PCB with wide,
copper filled areas.
3. Connect the ground of feedback divider and
compensation components directly to the GND
pin of the IC using a dedicated ground trace.
Then connect this pin as close as possible to the
ground of the output capacitor.
4. The VCC bypass capacitor should be right next
to the VCC and GND pins.
5. The trace connecting the feedback resistors to
the output should be short, direct and far away
from the switch node, and switching compo-
nents.
6. Minimize the trace between PDRV/NDRV
and the gates of the MOSFETs to reduce the
impedance driving the MOSFETs. This is espe-
cially important for the bottom MOSFET that
tends to turn on through its Miller capacitor
when the switch node swings high.
7. Minimize the loop composed of input capaci-
tors, top/bottom MOSFETs and Schottky diode.
This loop carries high di/dt current. Also in-
crease the trace width to reduce copper losses.
8. Maximize the trace width of the loop connect-
ing the inductor, output capacitors, Schottky
diode and bottom MOSFET.
9. ISET and ISENSE connections to Q1 for current
limiting must be make using Kelvin connec-
tions.
LAYOUT GUIDELINE



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