SP6123 datasheet(14/18 Pages) SIPEX

14 / 18 page

Date: 5/25/04

SP6123 Low Voltage, Synchronous Step Down PWM Controller

Most electrolytic and tantalum capacitors come

with adequate ESR value to generate a zero below

power supplies’ crossover frequency. This is cru-

cial to a stable close loop system. However, this

same system can become unstable if ceramic out-

put capacitors are used. The low ESR associated

with ceramic capacitors can push the ESR zero

above the crossover frequency and often higher

than 1MHz. In this case, type III compensation is

required to provide additional low frequency zero for

adequate phase margin and thus stable operation.

The design of type III compensation using

SP6123 transconductance error amplifier is quite

straightforward. First, the resonant frequency of

the LC output filter could be derived from

fr =

= 11.6kHz

π√ L1COUT

The values and references used in all the calcula-

tions agree with the schematic shown in Figure 3.

Select values of R2, C1, RZ and CZ to place two

zeros below or equal to the LC resonant fre-

quency. Those two zeros are located at:

fZ1 =

= 6kHz

πR2C1

fZ2 =

= 11.7kHz

πRZCZ

There is low frequency pole determined by both

the error amplifier gain and feedback gain. It

occurs at

fP1 =

= 3.25Hz

π(R2 // R3)CZGMROUT

In SP6123, GM (error amplifier transconductance)

and ROUT (error amplifier output impedance) are

specified at 0.6ms and 3M

Ω, respectively.

For frequencies above the second zero fZ2, the

feedback gain rises at 20dB/dec and is equal to

AFB = 2

πfRZC1

However, the error amplifier gain AEA declines

at -20dB/dec due to CP.

AEA =

πfCP

When AFB is less than AEA, the compensated

error amplifier gain is dominated by AFB. As a

result, it shows up as a positive 20dB/dec slope.

However, when the rising AFB crosses the fall-

ing AEA at one particular frequency, the com-

pensated error amplifier gain is now solely de-

termined by AEA. Therefore, the 20dB/dec slope

is converted to a -20dB/dec slope, and the bode

plot demonstrates a double pole at this fre-

quency which is equal to

fP2 =

1GM

= 221kHz

CPC1RZ

Select CP such that fP2 is located at least a decade

higher than the crossover frequency.

As shown in Figure 4, this type III compensation

generates a close loop system with 50 degree phase

margin and crossover frequency at 20kHz. This

ensures a stable regulated power supply with tight

DC regulation and fast transient response.

Figure 4. Bode Plot for schematic shown in Figure 3. V

IN = 3.3V and VOUT = 1.6V, no load.

-100

10Hz

100Hz

1.0kHz

10kHz

1.0MHz

10MHz

Gain

Phase

Frequency

200

100

-200

APPLICATIONS INFORMATION

SP6123 Datasheet(PDF) 14 Page - Sipex Corporation

SP6123 Datasheet(HTML) 14 Page - Sipex Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Datasheet Download

Link URL