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SP782 Datasheet(PDF) 9 Page - Sipex Corporation

Part # SP782
Description  Programmable Charge Pump
PDF  16 Pages
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Manufacturer  SIPEX [Sipex Corporation]
Direct Link  http://www.sipex.com
Logo SIPEX - Sipex Corporation

SP782 Datasheet(HTML) 9 Page - Sipex Corporation

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9
SP782/SP784 DS/08
SP782/784 Programmable Charge Pump
© Copyright 2000 Sipex Corporation
V
SS receives a continuous charge from either C1
or C
2. With the C1 capacitor charged to 5V, the
cycle begins again.
Phase 3
— V
DD charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C
1 produces –5V in the negative
terminal of C
1, which is applied to the negative
side of capacitor C
2. Since C2
+ is at +5V, the
voltage potential across C
2 is l0V. For the 5V
output, C
2
+ is connected to ground so that the
potential on C
2 is only +5V.
Phase 4
— V
DD transfer — The fourth phase of the
clock connects the negative terminal of C
2 to
ground and transfers the generated l0V or the
generated 5V across C
2 to C4, the VDD storage
capacitor. Again, simultaneously with this, the
positive side of capacitor C
1 is switched to +5V
and the negative side is connected to ground,
and the cycle begins again.
Since both V
DD and VSS are separately gener-
ated from V
CC in a no–load condition, VDD and
V
SS will be symmetrical. Older charge pump
approaches that generate V– from V+ will show
a decrease in the magnitude of V– compared to
V+ due to the inherent inefficiencies in the
design.
VCC = +5V
–5V
–5V
+5V
VDD Storage Capacitor
C1
C2
C4
+
++
–
–
–
VSS Storage Capacitor
C3
+
–
Figure 3. Charge Pump Phase 1 for
±5V.
VCC = +5V
+5V
VDD Storage Capacitor
C1
C2
C4
+
++
–
–
–
VSS Storage Capacitor
C3
+
–
–5V
Figure 2. Charge Pump Phase 1 for
±10V.
THEORY OF OPERATION
The SP782/784's charge pump design is based
on Sipex's original patented charge pump de-
sign (5,306,954) which uses a four–phase volt-
age shifting technique to attain symmetrical
10V power supplies. In addition, the SP782/
784 charge pump incorporates a "program-
mable" feature that produces an output of
±10V
or
±5V for V
SS and VDD by two control pins, D0
and D1. The charge pump requires external
capacitors to store the charge. Figure 1 shows
the waveform found on the positive and nega-
tive side of capcitor C2. There is a free–running
oscillator that controls the four phases of the
voltage shifting. A description of each phase
follows.
Phase 1 (
±10V)
— V
SS charge storage — During this phase of
the clock cycle, the positive side of capacitors
C
1 and C2 are initially charged to +5V. Cl
+ is
then switched to ground and the charge on C
1
–
is transferred to C
2
–. Since C
2
+ is connected to
+5V, the voltage potential across capacitor C
2
is now 10V.
Phase 1 (
±5V)
— V
SS & VDD charge storage and transfer —
With the C
1 and C2 capacitors initially charged
to +5V, C
l
+ is then switched to ground and the
charge on C
1
– is transferred to the V
SS storage
capacitor. Simultaneously the C
2
– is switched
to ground and 5V charge on C
2
+ is transferred
to the V
DD storage capacitor.
Phase 2 (
±10V)
— V
SS transfer — Phase two of the clock
connects the negative terminal of C
2 to the VSS
storage capacitor and the positive terminal of
C
2 to ground, and transfers the generated –l0V
or the generated –5V to C
3. Simultaneously,
the positive side of capacitor C
1 is switched to
+5V and the negative side is connected to
ground.
Phase 2 (
±5V)
— V
SS & VDD charge storage — C1
+ is
reconnected to V
CC to recharge the C1
capacitor. C
2
+ is switched to ground and C
2
– is
connected to C
3. The 5V charge from Phase 1 is
now transferred to the V
SS storage capacitor.



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