PWM

OUT_A

PGND

LM5026

OUT_A

OUT_B

OUT_A

OUT_B

N-Channel Active Clamp

P-Channel Active Clamp

LM5026

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SNVS363E – AUGUST 2005 – REVISED NOVEMBER 2015

Feature Description (continued)

Figure 14. PWM Output Phasing / Timing

The rising edge overlap or deadtime and the falling edge overlap or deadtime are identical and are independent

of operating frequency or duty cycle. The magnitude of the overlap/deadtime can be calculated in Equation 1 and

Equation 2:

where

•

•

overlap is in ns

(1)

.

where

•

•

deadtime is in ns

(2)

7.3.4 Gate Driver Outputs

The LM5026 provides two-gate driver outputs, the main power switch control (OUT_A) and the active clamp

switch control (OUT_B). The main gate driver features a compound configuration, consisting of both MOS and

bipolar devices, which provide superior gate drive characteristics. The bipolar device provides most of the drive

current capability and sinks a relatively constant current, which is ideal for driving large-power MOSFETs. As the

switching event nears conclusion and the bipolar device saturates, the internal MOS device provides a low

impedance to compete the switching event.

During turnoff at the Miller plateau region, typically between 2 V to 4 V, the voltage differential between the

output and PGND is small and the current source characteristic of the bipolar device is beneficial to reduce the

transition time. During turnon, the resistive characteristics of a purely MOS gate driver is adequate since the

supply to output voltage differential is fairly large in the Miller region.

Figure 15. Compound Gate Driver

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