LP3992 datasheet(15/23 Pages) TI1

15 / 23 page

GND

OUT

CAP

CIN

COUT

VIN

GND

VEN

VOUT

GND

LP3992

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SNVS192C – OCTOBER 2002 – REVISED NOVEMBER 2015

9.2.3 Application Curves

Figure 16. Load Transient Response

Figure 17. Load Transient Response

10 Power Supply Recommendations

The LP3992 is designed to operate from an input voltage supply range from 1.9 V to 5.2 V.

11 Layout

11.1 Layout Guidelines

The dynamic performance of the LP3992 is dependant on the layout of the PCB. PCB layout practices that are

adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the device.

Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP3992 and as close

as is practical to the package. The ground connections for CIN and COUT must be routed back to the LP3992

GND pin using as wide and as short a copper trace as is practical.

Avoid layout connections that have any combination of long trace length, narrow trace width, or vias. These add

parasitic inductances and resistance that result in inferior performance, especially during transient conditions.

11.2 Layout Example

Figure 18. LP3992 Layout Example

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LP3992 Datasheet(PDF) 15 Page - Texas Instruments