MICROWAVE CORPORATION

10 - 64

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10

GaAs HBT PROGRAMMABLE

5-BIT COUNTER, DC - 2.2 GHz

v04.1102

HMC394LP4

Synchronous Programming

For applications which can not tolerate a momentary undefined division ratio, which normally occurs while changing the

data bits (A0-A4) at random, synchronous programming can be used. Data is loaded into the counter on every rising

edge of the clock which occurs while the output (OUT) is “HIGH”. The typical minimum setup and hold times are shown

in the table below as a function of frequency. For precision applications, the rising edge of the complementary output

may be used to latch the new data bits (A0-A4), so that all bits are settled before the next load cycle.

T

Where N is the desired division ratio, and f

Programmable Divider Timing Requirements

for Synchronous Programming

IN

OUT

OUT

CURRENT DATA

NEW DATA

A0-A4

t

SU

t

HOLD

Data Load

Rising Edge

Rising Edge to

Clock New Data

Parameter

0.5 GHz

1 GHz

2 GHz

t

SETUP

200 ps

200 ps

200 ps

t

HOLD

700 ps

300 ps

120 ps