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PI6CFGL201B Datasheet(PDF) 1 Page - Pericom Semiconductor Corporation |
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PI6CFGL201B Datasheet(HTML) 1 Page - Pericom Semiconductor Corporation |
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1 / 14 page ![]() 1 www.pericom.com PI6CFGL201B RevB 03/16/16 All trademarks are property of their respective owners. PI6CFGL201B Block Diagram Description The PI6CFGL201B is a 2-output very low power 100MHz fre- quency generator for PCIe Gen 1, 2 and 3 applications with inte- grated output terminations providing Zo=100Ω. The device has 2 output enables for clock management and supports 2 different spread spectrum levels in addtion to spread off. The device also has one 1.8V LVCMOS REF1.8 output. Features Î Î 25MHz crystal or reference clock input Î Î 100MHz low power HCSL or LVDS compatible outputs Î Î PCIe 3.0, 2.0 and 1.0 compliant Î Î Selectable spread spectrum of -0.25%, -0.5% and no spread Î Î Programmable output amplitude and slew rate Î Î Cycle-to-cycle jitter (typ.) ~ 30ps Î Î Supply voltage of 3.3V+/-10% Î Î Output supply voltage of 1.8V (1.05V to 3.6V supported) Î Î Industrial ambient operating temperature Î Î Available in lead-free package: 24-TQFN 2-Output Low Power PCIE Gen 1-2-3 Clock Generator + I + u t OSC SDATA_3.3 SCLK_3.3 SS Capable PLL CONTROL LOGIC XTAL_IN or Ref CLK REF1.8 OE(1:0)# SADR SS_EN_tri CKPWRGD_PD# + CLK0 CLK0# CLK1 CLK1# XTAL_OUT Applications Î Î PCIe 3.0/2.0/1.0 clock generation Pin Configuration (24-Pin TQFN) 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 SADR/REF1.8 VDDREF1.8 GNDDIG CLK0 CLK0# GNDA VDDXTAL XTAL_OUT XTAL_IN CLK1# CLK1 VDDA3.3 15-0134 |
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