ADC12181EVAL datasheet(10/16 Pages) NSC

10 / 16 page

Specification Definitions (Continued)

FULL SCALE ERROR is the difference between the input

voltage just causing a transition to positive full scale and

REF -1.5 LSB.

INTEGRAL NON-LINEARITY (INL) is a measure of the de-

viation of each individual code from a line drawn from nega-

tive full scale (1⁄2 LSB below the first code transition) through

positive full scale (11⁄2 LSB above the last code transition).

The deviation of any given code from this straight line is

measured from the center of that code value.

INTERMODULATION DISTORTION (IMD) is the creation of

additional spectral components as a result of two sinusoidal

frequencies being applied to the ADC input at the same time.

It is defined as the ratio of the power in the intermodulation

products to the total power in the original frequencies. IMD is

usually expressed in dB.

PIPELINE DELAY (LATENCY) is the number of clock cycles

between initiation of conversion and the availability of that

conversion result at the output. New data is available at ev-

ery clock cycle, but the data lags the conversion by the pipe-

line delay.

SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SI-

NAD) is the ratio expressed in dB, of the rms value of the in-

put signal to the rms value of all of the other spectral compo-

nents below half the clock frequency, including harmonics

but excluding dc.

SIGNAL TO NOISE RATIO (SNR) is the ratio of the rms

value of the input signal to the rms value of the other spectral

components below one-half the sampling frequency, not in-

cluding harmonics or dc.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-

ence, expressed in dB, between the rms values of the input

signal and the peak spurious signal, where a spurious signal

is any signal present in the output spectrum that is not

present at the input.

TOTAL HARMONIC DISTORTION (THD) is the ratio of the

rms total of the first six harmonic components, to the rms

value of the input signal.

ZERO ERROR is the difference between the ideal input volt-

age (1⁄2 LSB) and the actual input voltage that causes an out-

put code transition from zero to one.

Timing Diagrams

DS101040-21

FIGURE 3. Data Output Timing

ADC12181EVAL Datasheet(PDF) 10 Page - National Semiconductor (TI)

ADC12181EVAL Datasheet(HTML) 10 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Datasheet Download

Link URL