ADC12662 datasheet(13/23 Pages) NSC

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Functional Description (Continued)

Voltage Estimator and 16 in the flash converter) is required

to quantize the input to 6 bits, instead of the 64 that would be

required using a traditional 6-bit flash.

Prior to a conversion, the Sample/Hold switch is closed,

allowing the voltage on the S/H capacitor to track the input

voItage. Switch 1 is in position 1. A conversion begins by

opening the Sample/Hold switch and latching the output of

the Voltage Estimator. The estimator decoder then selects

two adjacent banks of tap points aIong the MSB ladder.

These sixteen tap points are then connected to the sixteen

flash converters. For exampIe, if the input voltage is between

5/16 and 7/16 of V

REF (VREF =VREF+ −VREF−), the estimator

decoder instructs the comparator multiplexer to select the

sixteen tap points between 2/8 and 4/8 (4/16 and 8/16) of

REF and connects them to the sixteen flash converters. The

first flash conversion is now performed, producing the first 6

MSBs of data.

At this point, Voltage Estimator errors as large as 1/16 of

REF will be corrected since the flash converters are con-

nected to ladder voltages that extend beyond the range

specified by the Voltage Estimator. For example, if

(7/16)V

REF

< V

< (9/16)V

REF, the Voltage Estimator’s

comparators tied to the tap points below (9/16)V

REF will

output “1”s (000111). This is decoded by the estimator de-

coder to “10”. The 16 comparators will be placed on the MSB

ladder tap points between (3⁄8)V

REF and (

⁄8)V

REF. This over-

lap of (1/16)V

REF will automatically cancel a Voltage Estima-

tor error of up to 256 LSBs. If the first flash conversion

determines that the input voltage is between (3⁄8)V

REF and

((4/8)V

REF − LSB/2), the Voltage Estimator’s output code will

be corrected by subtracting “1”, resulting in a corrected value

of “01” for the first two MSBs. If the first flash conversion

determines that the input voltage is between (4/8)V

REF −

LSB/2) and (5⁄8)V

REF, the voltage estimator’s output code is

unchanged.

The results of the first flash and the Voltage Estimator’s

output are given to the factory-programmed on-chip EE-

PROM which returns a correction code corresponding to the

error of the MSB ladder at that tap. This code is converted to

a voltage by the Correction DAC. To generate the next four

bits, SW1 is moved to position 2, so the ladder voltage and

the correction voltage are subtracted from the input voltage.

The remainder is applied to the sixteen flash converters and

compared with the 16 tap points from the LSB ladder.

The result of this second conversion is accurate to 10 bits

and describes the input remainder as a voltage between two

tap points (V

H and VL) on the LSB ladder. To resolve the last

two bits, the voltage across the ladder resistor (between V

and V

L) is divided up into 4 equal parts by the capacitive

voltage divider, shown in

Figure 5. The divider also creates 6

LSBs below V

L and 6 LSBs above VH to provide overlap

used by the digital error correction. SW1 is moved to position

3, and the remainder is compared with these 16 new volt-

ages. The output is combined with the results of the Voltage

Estimator, first flash, and second flash to yield the final 12-bit

result.

By using the same sixteen comparators for all three flash

conversions, the number of comparators needed by the

multi-step converter is significantly reduced when compared

to standard multi-step techniques.

Applications Information

1.0 MODES OF OPERATION

The ADC12662 has two interface modes: An interrupt/read

mode and a high speed mode.

Figure 1 and 2 show the

timing diagrams for these interfaces.

In order to clearly show the relationship between S/H, CS,

RD, and OE, the control logic decoding section of the

ADC12662 is shown in

Figure 6.

Interrupt Interface

As shown in

Figure 1, the falling edge of S/H holds the input

voltage and initiates a conversion. At the end of the conver-

sion, the EOC output goes high and the INT output goes low,

indicating that the conversion results are latched and may be

read by pulling RD low. The falling edge of RD resets the INT

line. Note that CS must be low to enable S/H or RD.

High Speed Interface

The Interrupt interface works well at lower speeds, but few

microprocessors could keep up with the 1 µs interrupts that

would be generated if the ADC12662 was running at full

speed. The most efficient interface is shown in

Figure 2.

Here the output data is always present on the databus, and

the INT to RD delay is eliminated.

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