ADC12662 datasheet(19/23 Pages) NSC

19 / 23 page

Applications Information (Continued)

Figure 12 gives an example of a suitable layout, including

power supply routing, ground plane separation, and bypass

capacitor placement. All analog circuitry (input amplifiers,

filters, reference components, etc.) should be placed on the

analog ground plane. All digital circuitry and I/O lines (ex-

cluding the S/H input) should use the digital2 ground plane

as ground. The digital1 ground plane should only be used for

the S/H signal generation.

7.0 DYNAMIC PERFORMANCE

The ADC12662 is AC tested and its dynamic performance is

guaranteed. In order to meet these specifications, the clock

source driving the S/H input must be free of jitter. For the

best AC performance, a crystal oscillator is recommended.

For operation at or near the ADC12662’s 1.5 MHz maximum

sampling rate, a 1.5 MHz squarewave will provide a good

signal for the S/H input. As long as the duty cycle is near

50%, the waveform will be low for about 333 ns, which is

within the 400 ns limit. When operating the ADC12662 at a

sample rate of 1.25 MHz or below, the pulse width of the S/H

signal must be smaller than half the sample period.

Figure 13 is an example of a low jitter S/H pulse generator

that can be used with the ADC12662 and allow operation at

sampling rates from DC to 1.5 MHz. A standard 4-pin DIP

crystal oscillator provides a stable 1.5 MHz squarewave.

Since most DIP oscillators have TTL outputs, a 4.7k pullup

resistor is used to raise the output high voltage to CMOS

input levels. The output is fed to the trigger input (falling

edge) of an MM74HC4538 one-shot. The 1k resistor and

12 pF capacitor set the pulse length to approximately 100

ns. The S/H pulse stream for the converter appears on the Q

output of the HC4538. This is the S/H clock generator used

on the ADC12062EVAL evaluation board. For lower power, a

CMOS inverter-based crystal oscillator can be used in place

of the DIP crystal oscillator. See Application Note AN-340 in

the National Semiconductor CMOS Logic Databook for more

information on CMOS crystal oscillators.

8.0 COMMON APPLICATION PITFALLS

Driving inputs (analog or digital) outside power supply

rails. The Absolute Maximum Ratings state that all inputs

must be between GND − 300 mV and V

CC + 300 mV. This

rule is most often broken when the power supply to the

converter is turned off, but other devices connected to it (op

amps, microprocessors) still have power. Note that if there is

no power to the converter, DGND = AGND = DV

CC =AVCC

= 0V, so all inputs should be within ±300 mV of AGND and

DGND.

Driving a high capacitance digital data bus. The more

capacitance the data bus has to charge for each conversion,

the more instantaneous digital current required from DV

and DGND. These large current spikes can couple back to

the analog section, decreasing the SNR of the converter.

While adequate supply bypassing and separate analog and

digital ground planes will reduce this problem, buffering the

digital data outputs (with a pair of MM74HC541s, for ex-

ample) may be necessary if the converter must drive a

heavily loaded databus.

01187624

FIGURE 12. PC Board Layout

01187625

FIGURE 13. Crystal Clock Source

ADC12662 Datasheet(PDF) 19 Page - National Semiconductor (TI)

ADC12662 Datasheet(HTML) 19 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Datasheet Download

Link URL