MB9B110T datasheet(111/129 Pages) SPANSION

111 / 129 page

Da t a S h e e t

108

MB9B110T-DS706-00016-3v0-E, January 31, 2014

CONFIDENTIAL

12-bit A/D Converter

 Electrical characteristics for the A/D converter

(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40°C to + 85°C)

Parameter

Symbol

name

Value

Unit

Remarks

Min

Typ

Max

Resolution

bit

Integral Nonlinearity

± 4.5

LSB

AVRH = 2.7 V to

5.5 V

Differential Nonlinearity

± 2.5

LSB

Zero transition voltage

VZT

ANxx

± 15

Full-scale transition

voltage

VFST

ANxx

AVRH ± 15 mV

Conversion time

1.0*

μs

AVcc ≥ 4.5 V

1.2*

AVcc < 4.5 V

Sampling time

AVcc ≥ 4.5 V

AVcc < 4.5 V

Compare clock cycle*

Tcck

2000

State transition time to

operation permission

Tstt

1.0

μs

Analog input capacity

CAIN

12.9

Analog input resistance

RAIN

kΩ

AVcc ≥ 4.5 V

3.8

AVcc < 4.5 V

Interchannel disparity

LSB

Analog port input

current

ANxx

μA

Analog input voltage

ANxx

AVSS

AVRH

Reference voltage

AVRH

2.7

AVCC

*1: The Conversion time is the value of sampling time (Ts) + compare time (Tc).

The condition of the minimum conversion time is the following.

AVcc ≥ 4.5 V, HCLK=120 MHz

sampling time: 300 ns

compare time: 700 ns

AVcc < 4.5 V, HCLK=120 MHz

sampling time: 500 ns

compare time: 700 ns

Ensure that it satisfies the value of the sampling time (Ts) and compare clock cycle (Tcck).

For setting of the sampling time and compare clock cycle, see "CHAPTER 1-1: A/D Converter" in "FM3

Family PERIPHERAL MANUAL Analog Macro Part".

The registers setting of the A/D Converter are reflected in the operation according to the APB bus clock

timing.

The sampling clock and compare clock is generated from the Base clock (HCLK).

About the APB bus number which the A/D Converter is connected to, see "Block Diagram" in this data

sheet.

*2: A necessary sampling time changes by external impedance.

Ensure that it set the sampling time to satisfy (Equation 1).

*3: Compare time (Tc) is the value of (Equation 2).

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