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TAS5720L Datasheet(PDF) 21 Page - Texas Instruments |
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TAS5720L Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 52 page  D7 D0 ACK Stop Condition Acknowledge I CDevice Addressand 2 Read/WriteBit Subaddress LastDataByte A6 A5 A1 A0 R/W ACK A7 A5 A1 A0 ACK D7 ACK Start Condition Acknowledge Acknowledge Acknowledge FirstDataByte A4 A3 A6 OtherDataBytes ACK Acknowledge D0 D7 D0 T0036-02 A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK Start Condition Stop Condition Acknowledge Acknowledge Acknowledge I CDevice Addressand 2 Read/WriteBit Subaddress DataByte T0036-01 21 TAS5720L, TAS5720M www.ti.com SLOS903B – MAY 2015 – REVISED FEBRUARY 2016 Product Folder Links: TAS5720L TAS5720M Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated 7.3.2.1 Writing to the I2C Interface As shown Figure 40, a single-byte data-write transfer begins with the master device transmitting a start condition followed by the I2C bit and the read/write bit. The read/write bit determines the direction of the data transfer. For a data-write transfer, the read/write bit is a 0. After receiving the correct I2C bit and the read/write bit, the TAS5720L/M device responds with an acknowledge bit. Next, the master transmits the address byte corresponding to the TAS5720L/M device register being accessed. After receiving the address byte, the TAS5720L/M device again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5720L/M device again responds with an acknowledge bit. Lastly, the master device transmits a stop condition to complete the single- byte data-write transfer. Figure 40. Single Byte Write Transfer Timing A multi-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted as shown in Figure 41. After receiving each data byte, the TAS5720L/M device responds with an acknowledge bit. Sequential data bytes are written to sequential addresses. Figure 41. Multi-Byte Write Transfer Timing |
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