MB9DF565LLE datasheet(7/109 Pages) SPANSION

7 / 109 page

D at aS he e t

MB9D560_DS708-00001-3v0-E, May 15, 2015

CONFIDENTIAL

Function

Description

Reset control

−

Reset level

Hardware reset (system initialization)

Software reset (programing initialization)

−

Reset factor (Hardware reset )

Power-on reset (PONR), external reset input (RSTX, NMIX+RSTX), clock stop waiting with time-out reset,

low-voltage detection reset (internal low-voltage detection reset, 5V external low-voltage detection reset ),

watchdog reset (hardware watchdog reset, software watchdog reset ), clock supervisor reset (main clock

monitor, PLL clock monitor), software trigger hardware reset , profile error reset

−

Reset factor (software reset )

Software reset

Low power consumption control

−

Device state

RUN (Run State, CPU is operation status)

PSS (Power Saving State, CPU wait event from WFI)

−

Setting parameter of each devise state

Clock (clock source enable, clock source selection, clock divider, clock domain enable)

Clock monitor

Low-voltage detection

Memory protection unit (MPU)

−

Memory protection as master except processor

−

Target master

DMA controller

−

8 area

−

NMI generation when violation detection

Timing protection unit (TPU)

−

TPU 1 unit as CPU 1 unit

−

24-bit timer x 8 channels per unit

−

Support execution time protection, locking time protection, inter-arrival time protection, deadline protection

−

Support normal mode and over flow mode

−

Prescaler of each channels

Timer clock divider (1/1 to 1/64)

−

Independent prescaler of each channels

Timer clock divider (1/1, 1/2, 1/4, 1/16)

Clock supervisor (CSV)

−

Monitor target clock

Main oscillation input , main PLL output

−

Monitor method

Monitor of frequency range

−

Operation after error detection

Reset or NMI

Watchdog timer (WDT)

−

Watchdog timer embedded

Hardware watchdog timer

Software watchdog timer

−

Hardware watchdog timer

1 unit per system

32-bit watchdog timer with window function

Clock source: fast-CR or slow-CR

Set by boot program (BootROM maker)

Not set by user program

−

Software watchdog timer

1 unit per CPU

32-bit watchdog timer with window function

Clock source: fast-CR, slow-CR, main clock

One time set on user program (not set again)

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