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MB9DF565LLE Datasheet(PDF) 82 Page - SPANSION |
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MB9DF565LLE Datasheet(HTML) 82 Page - SPANSION |
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82 / 109 page  D at aS he e t May 15, 2015, MB9D560_DS708-00001-3v0-E 81 CONFIDENTIAL (5-1-4) SPI Compatible (SCR:SPI=1) and Serial Clock Output Signal Detect Level "L" (SMR:SCINV=1) (TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS=AVSS=RVSS=0.0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Serial clock cycle time tSCYC SCK0 to SCK4 Master mode (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) 4tCLK_PERI1 - ns SCK↓→SOT delay time tSLOVI SCK0 to SCK4, SOT0 to SOT4 -30 +30 ns Valid SIN→SCK↑ setup time tIVSHI SCK0 to SCK4, SIN0 to SIN4 30 - ns SCK↑→valid SIN hold time tSHIXI 0 - ns SOT→SCK↑ Delay time tSOVHI SCK0 to SCK4, SOT0 to SOT4 2tCLK_PERI1-30 - ns Serial clock "H" pulse width tSHSL SCK0 to SCK4, SOT0 to SOT4 Slave mode (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) tCLK_PERI1+10 - ns Serial clock "L" pulse width tSLSH 2tCLK_PERI1-10 - ns SCK↓→SOT delay time tSLOVE SCK0 to SCK4, SOT0 to SOT4 - 30 ns valid SIN→SCK↑ setup time tIVSHE SCK0 to SCK4, SIN0 to SIN4 10 - ns SCK↑→valid SIN hold time tSHIXE 20 - ns SCK fall time tF SCK0 to SCK4 - 5 ns SCK rise time tR SCK0 to SCK4 - 5 ns Transfer speed - - CL=50pF, IOL=-2mA, IOH=2mA - 5 Mbps - - CL=20pF, IOL=-1mA, IOH=1mA - 6 Mbps Notes: − This is the AC characteristic in CLK synchronized mode. − CL is the load capacitance applied to pins during testing. − The maximum baud rate is limited by the internal operation clock used and other parameters. See Hardware Manual for details. |
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