ADN2913 datasheet(16/37 Pages) AD

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ADN2913

Data Sheet

Rev. A | Page 16 of 37

Table 10. Control Register, CTRLB (Address 0x9)

Bits

Bit Name

Bit Description

SOFTWARE_RESET

Software reset. Write a 1 followed by a 0 to reset the device.

INIT_FREQ_ACQ

Initiate frequency acquisition. Write a 1 followed by a 0 to initiate a frequency acquisition

(optional).

CDR bypass

CDR bypass.

0 = CDR enabled.

1 = CDR bypassed.

LOL_CONFIG

LOL configuration.

0 = normal LOL.

1 = static LOL.

LOS_PDN

LOS power-down.

0 = normal LOS.

1 = LOS powered down.

LOS polarity

LOS polarity.

0 = active high LOS pin.

1 = active low LOS pin.

D1:D0

Reserved to 0.

Table 11. Control Register, CTRLC (Address 0xA)

Bits

Bit Name

Bit Description

D7:D3

Reserved to 0.

REFCLK_PDN

Reference clock power-down. Write a 0 to enable the reference clock.

Reserved to 0.

Reserved to 1.

Table 12. Lock to Reference Clock Mode Programming Register, LTR_MODE (Address 0xF)

Bits

Bit Name

Bit Description

Reserved to 0

LOL data

0 = valid recovered clock vs. reference clock during tracking

1 = valid recovered clock vs. data during tracking

D5:D4

FREF_RANGE[1:0]

fREF range

00 = 11.05 MHz to 22.1 MHz

01 = 22.1 MHz to 44.2 MHz

10 = 44.2 MHz to 88.4 MHz

11 = 88.4 MHz to 176.8 MHz

D3:D0

DATA_TO_REF_RATIO[3:0]

Data to reference ratio1 (N ≥ 2(N − 1), where N is the decimal equivalent of the binary code)

0000 = 1/2

0001 = 1

0010 = 2

0011 = 4

0100 = 8

…

1010 = 512

1 Data ÷ DIV_f

REF,

where DIV_fREF is the divided down reference referred to the 11.05 MHz to 22.1 MHz band (see the Reference Clock (Optional) section).

Data Rate/2(LTR_MODE[3:0] − 1) = REFCLK/2LTR_MODE[5:4]

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