ADN2913 datasheet(30/37 Pages) AD

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ADN2913

Data Sheet

Rev. A | Page 30 of 37

Disable Output Buffers

The ADN2913 provides the option of disabling the output buffers

for power savings. The clock output buffer can be disabled by

setting Bit CLKOUT_DISABLE (Bit D3 in Register 0x1E) = 1.

This setting reduces the total output power by 30 mW. For a total

of 60 mW of power savings, such as in a low power standby mode,

both the CLKOUT and DATOUT buffers can be disabled together

by setting DATOUT_DISABLE (Bit D4 in Register 0x1E) = 1.

INPUT CONFIGURATIONS

The ADN2913 input stage can work with the signal source in an

ac-coupled or dc-coupled configuration. The ADN2913 supports

one of the following input modes: limiting amplifier, equalizer,

or 0 dB EQ. The ADN2913 can be configured to use any required

input configuration through the I2C bus. Figure 31 shows a block

diagram of the input stage circuit.

The input signal path is configurable with the INPUT_SEL[1:0]

bits (Bits[D6:D5] in Register 0x16). Table 27 shows the

INPUT_SEL[1:0] bits and the input signal configuration.

LOS

DETECT

BYPASS

VCC

FLOAT

VREF

INPUT_SEL[1:0]

RX_TERM_FLOAT

LOS

NIN

50Ω

2.9kΩ

Figure 31. Input Stage Block Diagram

Table 27. Input Signal Configuration

Selected Input

INPUT_SEL[1:0]

RX_TERM_FLOAT = 0

RX_TERM_FLOAT = 1

Limiting Amplifier

VREF

Not defined

Equalizer

VREF

Not defined

0 dB EQ (0 dB Buffer)

VCC

Float

Not Defined

Not defined

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