AD7175-2 datasheet(21/63 Pages) AD

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Data Sheet

AD7175-2

Rev. A | Page 21 of 63

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The linear regulator for the digital IOVDD supply performs a

similar function, regulating the input voltage applied at the

IOVDD pin to 1.8 V for the internal digital filtering. The serial

interface signals always operate from the IOVDD supply seen at

the pin. This means that if 3.3 V is applied to the IOVDD pin,

the interface logic inputs and outputs operate at this level.

The AD7175-2 can be used across a wide variety of applications,

providing high resolution and accuracy. A sample of these

scenarios is as follows:

•

Fast scanning of analog input channels using the internal

multiplexer

•

Fast scanning of analog input channels using an external

multiplexer with automatic control from the GPIOs.

•

High resolution at lower speeds in either channel scanning

or ADC per channel applications

•

Single ADC per channel: the fast low latency output allows

further application specific filtering in an external micro-

controller, DSP, or FPGA

POWER SUPPLIES

The AD7175-2 has three independent power supply pins:

AVDD1, AVDD2, and IOVDD.

AVDD1 powers the crosspoint multiplexer and integrated analog

and reference input buffers. AVDD1 is referenced to AVSS, and

AVDD1 − AVSS = 5 V only. This can be a single 5 V supply or a

±2.5 V split supply. The split supply operation allows true

bipolar inputs. When using split supplies, consider the absolute

maximum ratings (see the Absolute Maximum Ratings section).

AVDD2 powers the internal 1.8 V analog LDO regulator. This

regulator powers the ADC core. AVDD2 is referenced to AVSS,

and AVDD2 − AVSS can range from 5.5 V (maximum) to 2 V

(minimum).

IOVDD powers the internal 1.8 V digital LDO regulator. This

regulator powers the digital logic of the ADC. IOVDD sets the

voltage levels for the SPI interface of the ADC. IOVDD is refer-

enced to DGND, and IOVDD − DGND can vary from 5.5 V

(maximum) to 2 V (minimum).

DIGITAL COMMUNICATION

The AD7175-2 has a 3- or 4-wire SPI interface that is compatible

with QSPI™, MICROWIRE®, and DSPs. The interface operates

in SPI Mode 3 and can be operated with CS tied low. In SPI

Mode 3, the SCLK idles high, the falling edge of SCLK is the

drive edge, and the rising edge of SCLK is the sample edge. This

means that data is clocked out on the falling/drive edge and data

is clocked in on the rising/sample edge.

Figure 45. SPI Mode 3 SCLK Edges

Accessing the ADC Register Map

The communications register controls access to the full register

map of the ADC. This register is an 8-bit write only register. On

power-up or after a reset, the digital interface defaults to a state

where it is expecting a write to the communications register;

therefore, all communication begins by writing to the

communications register.

The data written to the communications register determines

which register is being accessed and if the next operation is a

read or write. The register address bits (RA[5:0]) determine the

specific register to which the read or write operation applies.

When the read or write operation to the selected register is

complete, the interface returns to its default state, where it

expects a write operation to the communications register.

Figure 46 and Figure 47 illustrate writing to and reading from a

Figure 46. Writing to a Register (8-Bit Command with Register Address

Followed by Data of 8, 16, or 24 Bits;

Data Length on DIN Is Dependent on the Register Selected)

Figure 47. Reading from a Register (8-Bit Command with Register Address

Followed by Data of 8, 16, or 24 Bits;

Data Length on DOUT Is Dependent on the Register Selected)

DRIVE EDGE

SAMPLE EDGE

DIN

SCLK

8-BIT COMMAND

8 BITS, 16 BITS,

OR 24 BITS OF DATA

CMD

DATA

DIN

SCLK

8-BIT COMMAND

8 BITS, 16 BITS,

24 BITS, OR

32 BITS OUTPUT

CMD

DATA

DOUT/RDY

AD7175-2 Datasheet(PDF) 21 Page - Analog Devices

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