Data Sheet

AD9635

Rev. B | Page 25 of 36

Table 10. Flexible Output Test Modes

Output Test

Mode Bit

Sequence

Pattern Name

Digital Output Word 1

Digital Output Word 2

Subject to

Data Format

Select

Notes

0000

Off (default)

Not applicable

Not applicable

N/A

0001

Midscale short

10 0000 0000 (10-bit)

1000 0000 0000 (12-bit)

Not applicable

Yes

Offset binary

code shown

0010

+Full-scale short

11 1111 1111 (10-bit)

1111 1111 1111 (12-bit)

Not applicable

Yes

Offset binary

code shown

0011

−Full-scale short

00 0000 0000 (10-bit)

0000 0000 0000 (12-bit)

Not applicable

Yes

Offset binary

code shown

0100

Checkerboard

10 1010 1010 (10-bit)

1010 1010 1010 (12-bit)

01 0101 0101 (10-bit)

0101 0101 0101 (12-bit)

No

0101

Not applicable

Not applicable

Yes

PN23,

ITU 0.150

0110

Not applicable

Not applicable

Yes

PN9

ITU 0.150

0111

One-/zero-word toggle

11 1111 1111 (10-bit)

1111 1111 1111 (12-bit)

00 0000 0000 (10-bit)

0000 0000 0000 (12-bit)

No

1000

User input

Register 0x19 to Register 0x1A

Register 0x1B to Register 0x1C

No

1001

1-/0-bit toggle

10 1010 1010 (10-bit)

1010 1010 1010 (12-bit)

Not applicable

No

1010

1× sync

00 0011 1111 (10-bit)

0000 0111 1111 (12-bit)

Not applicable

No

1011

One bit high

10 0000 0000 (10-bit)

1000 0000 0000 (12-bit)

Not applicable

No

Pattern

associated

with the

external pin

1100

Mixed frequency

10 0011 0011 (10-bit)

1000 0110 0111 (12-bit)

Not applicable

No

1

All test mode options except PN sequence short and PN sequence long can support 10-bit to 12-bit word lengths to verify data capture to the receiver.

There are 12 digital output test pattern options available that

can be initiated through the SPI. This is a useful feature when

validating receiver capture and timing. Refer to Table 10 for the

output bit sequencing options available. Some test patterns have

two serial sequential words and can be alternated in various ways,

depending on the test pattern chosen.

Note that some patterns do not adhere to the data format select

option. In addition, custom user-defined test patterns can be

assigned in the 0x19, 0x1A, 0x1B, and 0x1C register addresses.

The PN sequence short pattern produces a pseudorandom bit

of the PN sequence and how it is generated can be found in

Section 5.1 of the ITU-T 0.150 (05/96) standard. The seed value

is all 1s (see Table 11 for the initial values). The output is a

parallel representation of the serial PN9 sequence in MSB-first

format. The first output word is the first 12 bits of the PN9

sequence in MSB aligned form.

Table 11. PN Sequence

Sequence

Initial Value

Next Three Output

Samples (MSB First),

Twos Complement

PN Sequence Short

0x7F8

0xBDF, 0x973, 0xA09

PN Sequence Long

0x7FF

0x7FE, 0x800, 0xFC0

The PN sequence long pattern produces a pseudorandom bit

description of the PN sequence and how it is generated can be

found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The

seed value is all 1s (see Table 11 for the initial values) and the

AD9635 inverts the bit stream with relation to the ITU standard.

The output is a parallel representation of the serial PN23 sequence

in MSB-first format. The first output word is the first 12 bits of the

PN23 sequence in MSB aligned form.

Consult the Memory Map section for information on how to

change these additional digital output timing features through

the SPI.