Functional Description

While the clock is LOW the slave is held steady and the

information on the D input is permitted to enter the master

The next transition from LOW to HIGH locks the master in

its present state making it insensitive to the D input This

transition simultaneously connects the slave to the master

causing the new information to appear on the outputs Mas-

ter and slave clock thresholds are internally offset in oppo-

site directions to avoid race conditions or simultaneous

master-slave changes when the clock has slow rise or fall

times

The CP and CE inputs are logically identical but physical

constraints associated with the Dual-In-Line package make

the CE input slower at the upper end of the toggle range To

prevent new data from entering the master on the next CP

LOW cycle CE should go HIGH while CP is still HIGH

TLF9890 – 4

FIGURE 1 Propagation Delay (CP to Q)

TLF9890 – 5

800 mV peak-to-peak sinewave input

FIGURE 2 Toggle Frequency Test Circuit

3