FM25V40-GC datasheet(9/23 Pages) CYPRESS

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PRELIMINARY

FM25V40

Document Number: 001-87288 Rev. *A

Page 9 of 23

Read Operation

After the falling edge of CS, the bus master can issue a READ

opcode. Following the READ command is a three-byte address

containing the 19-bit address (A18-A0) of the first byte of the

read operation. The upper five bits of the address are ignored.

After the opcode and address are issued, the device drives out

the read data on the next eight clocks. The SI input is ignored

during read data bytes. Subsequent bytes are data bytes, which

are read out sequentially. Addresses are incremented internally

as long as the bus master continues to issue clocks and CS is

LOW. If the last address of 7FFFFh is reached, the counter will

roll over to 00000h. Data is read MSB first. The rising edge of CS

terminates a read operation and tristates the SO pin. A read

operation is shown in Figure 12.

Fast Read Operation

The FM25V40 supports a FAST READ opcode (0Bh) that is

provided for code compatibility with serial flash devices. The

FAST READ opcode is followed by a three-byte address

containing the 19-bit address (A18-A0) of the first byte of the

read operation and then a dummy byte. The dummy byte inserts

a read latency of 8-clock cycle. The fast read operation is

otherwise the same as an ordinary read operation except that it

requires an additional dummy byte. After receiving opcode,

address, and a dummy byte, the FM25V40 starts driving its SO

line with data bytes, with MSB first, and continues transmitting

as long as the device is selected and the clock is available. In

case of bulk read, the internal address counter is incremented

automatically, and after the last address 7FFFFh is reached, the

counter rolls over to 00000h. When the device is driving data on

its SO line, any transition on its SI line is ignored. The rising edge

of CS terminates a fast read operation and tristates the SO pin.

A Fast Read operation is shown in Figure 13.

Figure 11. Memory Write (WREN not shown) Operation

Figure 12. Memory Read Operation

SCK

0123

20 21 22 23 01234567

MSB

LSB

Data

Opcode

001

A17

A18

A16

19-bit Address

MSB

LSB

HI-Z

SCK

456

20 21 22 23 0123

MSB

LSB

Data

Opcode

A17

A18

A16

19-bit Address

MSB

LSB

HI-Z

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