LMV710 datasheet(11/19 Pages) NSC

11 / 19 page

Application Note

1.0 SUPPLY BYPASSING

The application circuits in this datasheet do not show the

power supply connections and the associated bypass ca-

pacitors for simplification. When the circuits are built, it is

always required to have bypass capacitors. Ceramic disc

capacitors (0.1µF) or solid tantalum (1µF) with short leads,

and located close to the IC are usually necessary to prevent

interstage coupling through the power supply internal imped-

ance. Inadequate bypassing will manifest itself by a low

frequency oscillation or by high frequency instabilities.

Sometimes, a 10µF (or larger) capacitor is used to absorb

low frequency variations and a smaller 0.1µF disc is paral-

leled across it to prevent any high frequency feedback

through the power supply lines.

2.0 SHUTDOWN MODE

The LMV711 and LMV715 have a shutdown pin. To conserve

battery life in portable applications, they can be disabled

when the shutdown pin voltage is pulled low. For LMV711

during shutdown mode, the output stays at about 50mV from

the lower rail, and the current drawn from the power supply

is 0.2µA (typical). This makes the LMV711 an ideal solution

for power sensitive applications. For the LMV715 during

shutdown mode, the output will be “Tri-stated”.

The shutdown pin should never be left unconnected. In

applications where shutdown operation is not needed and

the LMV711 or LMV715 is used, the shutdown pin should be

connected to V

+. Leaving the shutdown pin floating will result

in an undefined operation mode and the device may oscillate

between shutdown and active modes.

3.0 RAIL-TO-RAIL INPUT

The rail-to-rail input is achieved by using paralleled PMOS

and NMOS differential input stages. (See Simplified Sche-

matics in this datasheet). When the common mode input

voltage changes from ground to the positive rail, the input

stage goes through three modes. First, the NMOS pair is

cutoff and the PMOS pair is active. At around 1.4V, both

PMOS and NMOS pairs operate, and finally the PMOS pair

is cutoff and NMOS pair is active. Since both input stages

have their own offset voltage (V

OS), the offset of the amplifier

becomes a function of the common-mode input voltage. See

curves for V

OS vs. VCM in curve section.

As shown in the curve, the V

OS has a crossover point at 1.4V

above V

−. Proper design must be done in both DC and AC

coupled applications to avoid problems. For large input sig-

nals that include the V

OS crossover point in their dynamic

range, it will cause distortion in the output signal. One way to

avoid such distortion is to keep the signal away from the

crossover point. For example, in a unity gain buffer configu-

ration and with V

S = 5V, a 3V peak-to-peak signal center at

2.5V will contain input-crossover distortion. To avoid this, the

input signal should be centered at 3.5V instead. Another way

to avoid large signal distortion is to use a gain of −1 circuit

which avoids any voltage excursions at the input terminals of

the amplifier. See Figure 1. In this circuit, the common mode

DC voltage (V

CM) can be set at a level away from the VOS

crossover point.

When the input is a small signal and this small signal falls

inside the V

OS transition range, the gain, CMRR and some

other parameters will be degraded. To resolve this problem,

the small signal should be placed such that it avoids the V

crossover point.

To achieve maximum output swing, the output should be

biased at mid-supply. This is normally done by biasing the

input at mid-supply. But with supply voltage range from 2V to

3.4V, the input of the op amp should not be biased at

mid-supply because of the transition of the V

OS. Figure 2

shows an example of how to get away from the V

OS cross-

over point and maintain a maximum swing with a 2.7V

supply. Figure 3 shows the waveforms of V

IN and VOUT.

The inputs can be driven 300mV beyond the supply rails

without causing phase reversal at the output. However, the

inputs should not be allowed to exceed the maximum rat-

ings.

10132552

FIGURE 1.

10132517

FIGURE 2.

10132551

FIGURE 3.

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