CLC5665IM datasheet(5/8 Pages) NSC

5 / 8 page

2nd and 3rd Harmonic Distortion

To meet low distortion requirements, recognize the effect

of the feedback resistor.

Increasing the feedback

resistor will decrease the loop gain and increase

distortion. Decreasing the load impedance increases 3rd

harmonic distortion more than 2nd.

Differential Gain and Differential Phase

The CLC5665 has low DG and DP errors for video

applications. Add an external pulldown resistor to the

CLC5665’s output to improve DG and DP as seen in

Figure 4. A 604

Ω R

p will improve DG and DP to 0.01%

and 0.02°.

Figure 4: Improved DG and DP Video Amplifier

Printed Circuit Layout

To get the best amplifier performance careful placement

of the amplifier, components and printed circuit traces

must be observed. Place the 0.1

µF ceramic decoupling

capacitors less than 0.1” (3mm) from the power supply

pins.

Place the 6.8

µF tantalum capacitors less than

0.75” (20mm) from the power supply pins. Shorten traces

between the inverting pin and components to less

than 0.25” (6mm). Clear ground plane 0.1” (3mm) away

from pads and traces that connect to the inverting, non-

inverting and output pins. Do not place ground or power

plane beneath the op-amp package. National provides

literature and evaluation boards CLC730013 DIP or

CLC730027 SOIC illustrating the recommended op-amp

layout.

Level Shifting

The circuit shown in Figure 5 implements level shifting by

AC coupling the input signal and summing a DC voltage.

The resistor Rin and the capacitor C set the high-pass

break frequency. The amplifier closed-loop bandwidth is

fixed by the selection of Rf. The DC and AC gains for

circuit of Figure 5 are different. The AC gain is set by the

ratio of Rf and Rg. And the DC gain is set by the parallel

combination of Rg and R2.

Figure 5: Level Shifting Circuit

Multiplexing

Multiple signal switching is easily handled with the dis-

able function of the CLC5665. Board trace capacitance

at the output pin will affect the frequency response and

switching transients. To lessen the effects of output

capacitance place a resistor (Ro) within the feedback

loop to isolate the outputs as shown in Figure 6. To match

the mux output impedance to a transmission line, add a

resistor (Rs) in series with the output.

Figure 6: Output Connection for

Multiplexing Circuits

Differential Line Driver With Load

Impedance Conversion

The circuit shown in Figure 7, operates as a differential

line driver. The transformer converts the load impedance

to a value that best matches the CLC5665’s output

capabilities. The single-ended input signal is converted

to a differential signal by the CLC5665. The line’s

characteristic impedance is matched at both the input

and the output. The schematic shows Unshielded Twisted

Pair for the transmission line; other types of lines can also

be driven.

Figure 7: Differential Line Driver with

Load Impedance Conversion

http://www.national.com

Vin

-Vcc

Vout

Add R to

improve

DG and DP

Rin

CLC5665

Applications Circuits

out























 −









Vin

Vout

Rin

CLC5665

Rin

Vout

Vin1

Vin2

DIS1

DIS2

CLC5665

Rg2

Rt2

Rf2

Rf1

Rg1

CLC5665

Vin

Rt1

Rm/2

UTP

Req

1:n

Vd/2

-Vd/2

CLC5665IM Datasheet(PDF) 5 Page - National Semiconductor (TI)

CLC5665IM Datasheet(HTML) 5 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8

Datasheet Download

Link URL