Electronic Components Datasheet Search
  English  ▼

X  

COP688CL Datasheet(PDF) 11 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # COP688CL
Description  General Description
PDF  40 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

COP688CL Datasheet(HTML) 11 Page - National Semiconductor (TI)

Back Button COP688CL Datasheet HTML 7Page - National Semiconductor (TI) COP688CL Datasheet HTML 8Page - National Semiconductor (TI) COP688CL Datasheet HTML 9Page - National Semiconductor (TI) COP688CL Datasheet HTML 10Page - National Semiconductor (TI) COP688CL Datasheet HTML 11Page - National Semiconductor (TI) COP688CL Datasheet HTML 12Page - National Semiconductor (TI) COP688CL Datasheet HTML 13Page - National Semiconductor (TI) COP688CL Datasheet HTML 14Page - National Semiconductor (TI) COP688CL Datasheet HTML 15Page - National Semiconductor (TI) Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 40 page
background image
AC Electrical Characteristics (Continued)
TLDD9766 – 26
FIGURE 2 MICROWIREPLUS Timing
Pin Descriptions
VCC and GND are the power supply pins
CKI is the clock input This can come from an RC generat-
ed oscillator or a crystal oscillator (in conjunction with
CKO) See Oscillator Description section
RESET is the master reset input See Reset Description
section
The device contains three bidirectional 8-bit IO ports (C G
and L) where each individual bit may be independently con-
figured as an input (Schmitt trigger inputs on ports G and L)
output or TRI-STATE under program control Three data
memory address locations are allocated for each of these I
O ports Each IO port has two associated 8-bit memory
mapped registers the CONFIGURATION register and the
output DATA register A memory mapped address is also
reserved for the input pins of each IO port (See the memo-
ry map for the various addresses associated with the IO
ports)
Figure 3 shows the IO port configurations The
DATA and CONFIGURATION registers allow for each port
bit to be individually configured under software control as
shown below
CONFIGURATION
DATA
Port Set-Up
Register
Register
0
0
Hi-Z Input
(TRI-STATE Output)
0
1
Input with Weak Pull-Up
1
0
Push-Pull Zero Output
1
1
Push-Pull One Output
TLDD9766 – 6
FIGURE 3 IO Port Configurations
PORT L is an 8-bit IO port All L-pins have Schmitt triggers
on the inputs
Port L supports Multi-Input Wakeup (MIWU) on all eight
pins L4 and L5 are used for the timer input functions T2A
and T2B
Port L has the following alternate features
L0
MIWU
L1
MIWU
L2
MIWU
L3
MIWU
L4
MIWU or T2A
L5
MIWU or T2B
L6
MIWU
L7
MIWU
Port G is an 8-bit port with 5 IO pins (G0 G2 – G5) an input
pin (G6) and two dedicated output pins (G1 and G7) Pins
G0 and G2 – G6 all have Schmitt Triggers on their inputs Pin
G1 serves as the dedicated WDOUT WATCHDOG output
while pin G7 is either input or output depending on the oscil-
lator mask option selected With the crystal oscillator option
selected G7 serves as the dedicated output pin for the CKO
clock output With the single-pin RC oscillator mask option
selected G7 serves as a general purpose input pin but is
also used to bring the device out of HALT mode with a low
to high transition There are two registers associated with
the G Port a data register and a configuration register
Therefore each of the 5 IO bits (G0 G2 – G5) can be indi-
vidually configured under software control
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin or general purpose input (RC clock config-
uration) the associated bits in the data and configuration
registers for G6 and G7 are used for special purpose func-
tions as outlined below Reading the G6 and G7 data bits
will return zeros
Note that the chip will be placed in the HALT mode by writ-
ing a ‘‘1’’ to bit 7 of the Port G Data Register Similarly the
chip will be placed in the IDLE mode by writing a ‘‘1’’ to bit 6
of the Port G Data Register
Writing a ‘‘1’’ to bit 6 of the Port G Configuration Register
enables the MICROWIREPLUS to operate with the alter-
nate phase of the SK clock The G7 configuration bit if set
high enables the clock start up delay after HALT when the
RC clock configuration is used
Config Reg
Data Reg
G7
CLKDLY
HALT
G6
Alternate SK
IDLE
Port G has the following alternate features
G0
INTR (External Interrupt Input)
G2
T1B (Timer T1 Capture Input)
G3
T1A (Timer T1 IO)
G4
SO (MICROWIRETM Serial Data Output)
G5
SK (MICROWIRE Serial Clock)
G6
SI (MICROWIRE Serial Data Input)
http
www nationalcom
11



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com