AD8330 datasheet(18/28 Pages) AD

18 / 28 page

REV. A

–18–

AD8330

Offset Compensation

The AD8330 includes an offset compensation feature, which is

operational in the default condition (no connection to pin OFST).

This loop introduces a high-pass filter function into the signal

path, whose –3 dB corner frequency is at:

fHPF = ()

π RC

INT

(11)

where CHP is the external capacitance added from OFST to CNTR,

and RINT is an internal resistance of approximately 480

Ω, having a

maximum uncertainty of about

±20%. This evaluates to:

fHPF ≈

()

330

Cin F

(12)

A small amount of peaking at this corner when using small capacitor

values can be avoided by adding a series resistor. Useful combina-

tions are CHP = 3 nF, RHP = 180

Ω , f = 100 kHz; C

HP = 33 nF,

RHP = 10

Ω, f = 10 kHz; CHP = 0.33 µF, RHP = 0 Ω, f = 1 kHz;

CHP = 3.3

µF, RHP = 0 Ω , f = 100 Hz.

The offset compensation feature can be disabled simply by ground-

ing the OFST pin. This provides a dc-coupled signal path, with

no other effects on the overall ac response. Input offsets must be

externally nulled in this mode of operation, as shown in Figure 15.

Effects of Loading on Gain and AC Response

The differential output impedance RO is 150

Ω and the frequency

response of the output stage is optimized for operation with a certain

load capacitance on each output pin, OPHI and OPLO, to

ground, in combination with a load resistance RL directly across

these pins. In the absence of these capacitances, there will be a

small amount of peaking at the top extremity of the ac response.

Suitable combinations are: RL =

∞, C

L = 12 pF; RL = 150

Ω,

CL = 25 pF; RL = 75

Ω, CL = 40 pF; RL = 50 Ω, CL = 50 pF.

The gain calibration is specified for an open-circuited load, such

as the high input resistance of an ADC. When resistively loaded,

all gain values are nominally lowered as follows:

LOADED

UNLOADED

()

150

Ω

(13)

Thus when RL = 150

Ω, the gain is reduced by 6 dB; for RL = 75 Ω,

the reduction is 9.5 dB; and for RL = 50

Ω, it is 12 dB.

Gain Errors Due to On-Chip Resistor Tolerances

In all cases where external resistors are used, keep in mind that all

on-chip resistances, including the RO and the input resistance,

RI, are subject to variances of up to

±20%, which will need to

be accounted for when calculating the gain with input and output

loading. This sensitivity can be avoided by adjusting the source

and load resistances to bear an inverse relationship as follows:

If RS =

αRI then make RL = RO /α; or, if RL = αRO then make

RS = RI /

α. The simplest case is when RS = 1 kΩ and RL = 150 Ω.

Here the gain is 12 dB lower than the basic value. The reduction

of peak swing at the load can be corrected by using VMAG = 1 V,

which also restores 6 dB of gain; using VMAG = 2 V restores the

full basic gain while also doubling the peak available output swing.

Output (Input) Common-Mode Control

The output voltages are nominally positioned at the midpoint of

the supply, VS/2, over the range 2.7 V < VS < 6 V, and this voltage

appears at pin CNTR, which is not normally expected to be

loaded (the source resistance is ~4 k

Ω). However, some circum-

stances may require a small change in this voltage, and a resistor

from CNTR to ground can lower this voltage, or one to the supply

will raise it. On the other hand, this pin may be driven by an

external voltage source to set the common-mode level, to satisfy

the needs of a following ADC, for example. Any value from 0.5 V

above ground to 0.5 V below the supply is permissible. Of

course, when using an extreme common-mode level, the avail-

able output swing will be limited, and it is recommended that a

value equal or close to the default of VCNTR = VS/2 be used. There

may be a few millivolts of offset between the applied voltage and the

actual common-mode level at the output pins.

The input common-mode voltage VCMI at pins INHI, INLO is

slaved to the output, but with a shifted value:

CMI

0 757

1 12

CNTR

(14)

for VDBS = 0.75 and T = 25

°C. Thus, the default value for V

CMI

when VS = 5 V is 3.01 V (see Figure 12).

USING THE AD8330

There are very few precautions that need to be observed in apply-

ing the AD8330 to a wide variety of circumstances. A selection

of specific applications is presented later. Here we discuss a few

general aspects of utilization.

As in all high frequency circuits, careful observation of the ground

nodes associated with each function is important. Three positive

supply pins are provided. VPSI supports the input circuitry, which

may often be operating at a relatively high sensitivity; VPOS,

which supports general bias sources, needs no decoupling; VPSO

is used to bias the output stage, where decoupling may be useful

in maintaining a glitch-free output. Figure 14 shows the general

case, where VPSI and VPSO are each provided with their own

decoupling network, but this may not be needed in all cases.

Because of the differential nature of the signal path, power-supply

decoupling is in general much less critical than in a single-sided

amplifier, and where the minimization of board-level components

is especially crucial, it may be found that these pins need no

decoupling at all. On the other hand, when the signal source is

COMM

OPHI

INLO

OPLO

INHI

VPSI

VPSO

CMOP

MODE

VDBS

CMGN

VMAG

OFST

ENBL

CNTR

VPOS

BIAS AND

V-REF

GAIN INTERFACE

CM MODE AND

OFFSET CONTROL

OUTPUT

STAGES

OUTPUT

CONTROL

VGA CORE

OUTPUT,

2V MAX

BASIC GAIN BIAS

VDBS: 0V TO 1.5V

RD1

CHPF

CD2

CD1

CD3

RD2

GROUND

VS 2.7V–6V

INPUT,

0V TO 2V MAX

Figure 14. Power Supply Decoupling and Basic Connections

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