AT45CS1282 datasheet(6/33 Pages) ATMEL

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AT45CS1282 [Preliminary]

3447A–DFLSH–2/04

Additional Commands

MAIN MEMORY PAGE TO BUFFER TRANSFER: A page of data can be transferred

from the main memory to either buffer 1 or buffer 2. To start the operation, a 1-byte

opcode, 53H for buffer 1 and 55H for buffer 2, must be clocked into the device, followed

by four address bytes comprised of 7 don’t care bits, 14-page address bits (PA13- PA0),

which specify the page in main memory that is to be transferred, and 11 don’t care bits.

The CS pin must be low while toggling the SCK/CLK pin to load the opcode and the

address bytes from the input pins (SI or I/O7 - I/O0). The transfer of the page of data

from the main memory to the buffer will begin when the CS pin transitions from a low to

a high state. During the transfer of a page of data (t

XFR), the status register can be read

or the RDY/BUSY can be monitored to determine whether the transfer has been

completed.

MAIN MEMORY PAGE TO BUFFER COMPARE: A page of data in main memory can

be compared to the data in buffer 1 or buffer 2. To initiate the operation, a 1-byte

opcode, 60H for buffer 1 and 61H for buffer 2, must be clocked into the device, followed

by four address bytes consisting of 7 don’t care bits, 14-page address bits (PA13 - PA0)

that specify the page in the main memory that is to be compared to the buffer, and 11

don’t care bits. The CS pin must be low while toggling the SCK/CLK pin to load the

opcode and the address bytes from the input pins (SI or I/O7 - I/O0). On the low-to-high

transition of the CS pin, the 1056 bytes in the selected main memory page will be com-

pared with the 1056 bytes in buffer 1 or buffer 2. During this time (t

XFR), the status

compare operation, bit 6 of the status register is updated with the result of the compare.

STATUS REGISTER READ: The status register can be used to determine the device’s

ready/busy status, the result of a Main Memory Page to Buffer Compare operation, or

the device density. To read the status register, an opcode must be loaded into the

device. After the opcode and optional dummy byte(s) is clocked in, the 1-byte status

clock cycle. In case of serial interface, opcode D7H is followed with an optional dummy

byte (8 clocks). For Serial applications over 25 MHz, opcode must be always followed

with a dummy byte. In case of applications with 8-bit interface, opcode D7H and two

dummy clock cycles should be used. When using the serial interface, the data in the sta-

tus register, starting with the MSB (bit 7), will be clocked out on the SO pin during the

next eight clock cycles.

Sector Erase Addressing

PA13

PA12

PA11

PA10

PA9

PA8

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

Sector

000

000000

XXXXX

•

XXXXX

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