COP884CF datasheet(32/44 Pages) NSC

32 / 44 page

MICROWIRE/PLUS

MICROWIRE/PLUS is a serial synchronous communications

interface. The MICROWIRE/PLUS capability enables the de-

vice to interface with any of National Semiconductor’s MI-

CROWIRE peripherals (i.e. A/D converters, display drivers,

2PROMs etc.) and with other microcontrollers which sup-

port the MICROWIRE interface. It consists of an 8-bit serial

shift register (SIO) with serial data input (SI), serial data out-

put (SO) and serial shift clock (SK).

Figure 16 shows a block

diagram of the MICROWIRE/PLUS logic.

The shift clock can be selected from either an internal source

or an external source. Operating the MICROWIRE/PLUS ar-

rangement with the internal clock source is called the Master

mode of operation. Similarly, operating the MICROWIRE/

PLUS arrangement with an external shift clock is called the

Slave mode of operation.

The CNTRL register is used to configure and control the

MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,

the MSEL bit in the CNTRL register is set to one. In the mas-

ter mode the SK clock rate is selected by the two bits, SL0

and SL1, in the CNTRL register.

Table 7 details the different

clock rates that may be selected.

TABLE 7. MICROWIRE/PLUS

Master Mode Clock Selection

SL1

SL0

2xt

4xt

8xt

Where t

c is the instruction cycle clock

MICROWIRE/PLUS OPERATION

Setting the BUSY bit in the PSW register causes the

MICROWIRE/PLUS to start shifting the data. It gets reset

when eight data bits have been shifted. The user may reset

the BUSY bit by software to allow less than 8 bits to shift. If

enabled, an interrupt is generated when eight data bits have

been shifted. The device may enter the MICROWIRE/PLUS

mode either as a Master or as a Slave.

Figure 17 shows how

two COP888CF microcontrollers and several peripherals

may be interconnected using the MICROWIRE/PLUS ar-

rangements.

Warning:

The SIO register should only be loaded when the SK clock is

low. Loading the SIO register while the SK clock is high will

result in undefined data in the SIO register. SK clock is nor-

mally low when not shifting.

Setting the BUSY flag when the input SK clock is high in the

MICROWIRE/PLUS slave mode may cause the current SK

clock for the SIO shift register to be narrow. For safety, the

BUSY flag should only be set when the input SK clock is low.

MICROWIRE/PLUS Master Mode Operation

In the MICROWIRE/PLUS Master mode of operation the

shift clock (SK) is generated internally. The MICROWIRE

Master always initiates all data exchanges. The MSEL bit in

the CNTRL register must be set to enable the SO and SK

functions onto the G Port. The SO and SK pins must also be

selected as outputs by setting appropriate bits in the Port G

configuration register.

Table 8 summarizes the bit settings

required for Master mode of operation.

DS009425-20

FIGURE 16. MICROWIRE/PLUS Block Diagram

DS009425-21

FIGURE 17. MICROWIRE/PLUS Application

COP884CF Datasheet(PDF) 32 Page - National Semiconductor (TI)

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