COP884CF datasheet(22/44 Pages) NSC

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A/D Converter (Continued)

A/D Control Register

A control register, Reg: ENAD, contains 3 bits for channel se-

lection, 3 bits for prescaler selection, and 2 bits for mode se-

lection. An A/D conversion is initiated by writing to the ENAD

control register. The result of the conversion is available to

the user from the A/D result register, Reg: ADRSLT.

Reg: ENAD

CHANNEL

SELECT

MODE

SELECT

PRESCALER

SELECT

Bits 7, 6, 5

Bits 4,3

Bits 2, 1, 0

CHANNEL SELECT

This 3-bit field selects one of eight channels to be the V

IN+.

The mode selection determines the V

IN− input.

Single Ended mode:

Bit 7

Bit 6

Bit 5

Channel No.

000

001

010

011

100

101

110

111

Differential mode:

Bit 7

Bit 6

Bit 5

Channel Pairs (+. −)

000

0, 1

001

1, 0

010

2, 3

011

3, 2

100

4, 5

101

5, 4

110

6, 7

111

7, 6

MODE SELECT

This 2-bit field is used to select the mode of operation (single

conversion, continuous conversions, differential, single

ended) as shown in the following table.

Bit 4

Bit 3

Mode

Single Ended mode, single conversion

Single Ended mode, continuous scan

of a single channel into the result

Differential mode, single conversion

Differential mode, continuous scan of

a channel pair into the result register

PRESCALER SELECT

This 3-bit field is used to select one of the seven prescaler

clocks for the A/D converter. The prescaler also allows the

A/D clock inhibit power saving mode to be selected. The fol-

lowing table shows the various prescaler options.

Bit 2

Bit 1

Bit 0

Clock Select

Inhibit A/D clock

Divide by 1

Divide by 2

Divide by 4

Divide by 6

Divide by 12

Divide by 8

Divide by 16

ADC Operation

The A/D converter interface works as follows. Writing to the

A/D control register ENAD initiates an A/D conversion unless

the prescaler value is set to 0, in which case the ADC clock

is stopped and the ADC is powered down. The conversion

sequence starts at the beginning of the write to ENAD opera-

tion powering up the ADC. At the first falling edge of the con-

verter clock following the write operation (not counting the

falling edge if it occurs at the same time as the write opera-

tion ends), the sample signal turns on for two clock cycles.

The ADC is selected in the middle of the sample period. If the

ADC is in single conversion mode, the conversion complete

signal from the ADC will generate a power down for the A/D

converter. If the ADC is in continuous mode, the conversion

complete signal will restart the conversion sequence by de-

selecting the ADC for one converter clock cycle before start-

ing the next sample. The ADC 8-bit result is loaded into the

A/D result register (ADRSLT) except during LOAD clock

high, which prevents transient data (resulting from the ADC

writing a new result over an old one) being read from

ADRSLT.

Inadvertant changes to the ENAD register during conversion

are prevented by the control logic of the A/D. Any attempt to

write any bit of the ENAD Register except ADBSY, while

ADBSY is a one, is ignored. ADBSY must be cleared either

by completion of an A/D conversion or by the user before the

prescaler, conversion mode or channel select values can be

changed. After stopping the current conversion, the user can

load different values for the prescaler, conversion mode or

channel select and start a new conversion in one instruction.

It is important for the user to realize that, when used in differ-

ential mode, only the positive input to the A/D converter is

sampled and held. The negative input is constantly con-

nected and should be held stable for the duration of the con-

version. Failure to maintain a stable negative input will result

in incorrect conversion.

PRESCALER

The A/D Converter (ADC) contains a prescaler option which

allows seven different clock selections. The A/D clock fre-

quency is equal to CKI divided by the prescaler value. Note

that the prescaler value must be chosen such that the A/D

clock falls within the specified range. The maximum A/D fre-

quency is 1.67 MHz. This equates to a 600 ns ADC clock

cycle.

The A/D converter takes 12 ADC clock cycles to complete a

conversion. Thus the minimum ADC conversion time for the

device is 7.2 µs when a prescaler of 6 has been selected.

These 12 ADC clock cycles necessary for a conversion con-

COP884CF Datasheet(PDF) 22 Page - National Semiconductor (TI)

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