ISP1160BMSLASH01 datasheet(13/88 Pages) PHILIPS

13 / 88 page

Philips Semiconductors

ISP1160

Embedded USB Host Controller

Product data

Rev. 04 — 04 July 2003

13 of 88

9397 750 11371

In Figure 10 and Figure 11, the DMA transfer is conﬁgured such that DREQ is active

HIGH and DACK_N is active LOW.

8.6 Interrupts

The ISP1160 has an interrupt request pin INT.

8.6.1

Pin conﬁguration

The interrupt output signals have four conﬁguration modes:

Mode 0

Mode 0 level trigger, active LOW

Mode 1

Mode 1 level trigger, active HIGH

Mode 2

Mode 2 edge trigger, active LOW

Mode 3

Mode 3 edge trigger, active HIGH.

= 1/2 byte count of transfer data.

Fig 10. DMA transfer in single-cycle mode.

004aaa368

DREQ

DACK_N

D[15:0]

EOT

data #1

data #2

data #N

RD_N or

WR_N

= 1/2 byte count of transfer data, K = number of cycles/burst.

Fig 11. DMA transfer in burst mode.

004aaa369

data #1

data #K

data #2K

data #N

data #(K

+1)

data #(N

−K+1)

DREQ

DACK_N

D[15:0]

EOT

RD_N or

WR_N

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