COP888CS datasheet(24/53 Pages) NSC

24 / 53 page

Multi-Input Wakeup (Continued)

If the L port bits have been used as outputs and then

changed to inputs with Multi-Input Wakeup/Interrupt, a safety

procedure should also be followed to avoid wakeup condi-

tions. After the selected L port bits have been changed from

output to input but before the associated WKEN bits are en-

abled, the associated edge select bits in WKEDG should be

set or reset for the desired edge selects, followed by the as-

sociated WKPND bits being cleared.

This same procedure should be used following reset, since

the L port inputs are left floating as a result of reset.

The occurrence of the selected trigger condition for

Multi-Input Wakeup is latched into a pending register called

WKPND. The respective bits of the WKPND register will be

set on the occurrence of the selected trigger edge on the cor-

responding Port L pin. The user has the responsibility of

clearing these pending flags. Since WKPND is a pending

the device will not enter the HALT mode if any Wakeup bit is

both enabled and pending. Consequently, the user must

clear the pending flags before attempting to enter the HALT

mode.

WKEN, WKPND and WKEDG are all read/write registers,

and are cleared at reset.

PORT L INTERRUPTS

Port L provides the user with an additional eight fully select-

able, edge sensitive interrupts which are all vectored into the

same service subroutine.

The interrupt from Port L shares logic with the wake up cir-

cuitry. The register WKEN allows interrupts from Port L to be

individually enabled or disabled. The register WKEDG speci-

fies the trigger condition to be either a positive or a negative

edge. Finally, the register WKPND latches in the pending

trigger conditions.

The GIE (Global Interrupt Enable) bit enables the interrupt

function.

A control flag, LPEN, functions as a global interrupt enable

for Port L interrupts. Setting the LPEN flag will enable inter-

rupts and vice versa. A separate global pending flag is not

needed since the register WKPND is adequate.

Since Port L is also used for waking the device out of the

HALT or IDLE modes, the user can elect to exit the HALT or

IDLE modes either with or without the interrupt enabled. If he

elects to disable the interrupt, then the device will restart ex-

ecution from the instruction immediately following the in-

struction that placed the microcontroller in the HALT or IDLE

modes. In the other case, the device will first execute the in-

terrupt service routine and then revert to normal operation.

(See HALT MODE for clock option wakeup information.)

The Wakeup signal will not start the chip running immedi-

ately since crystal oscillators or ceramic resonators have a fi-

nite start up time. The IDLE Timer (T0) generates a fixed de-

lay to ensure that the oscillator has indeed stabilized before

allowing the device to execute instructions. In this case,

upon detecting a valid Wakeup signal, only the oscillator cir-

cuitry and the IDLE Timer T0 are enabled. The IDLE Timer is

loaded with a value of 256 and is clocked from the t

c instruc-

tion cycle clock. The t

c clock is derived by dividing down the

oscillator clock by a factor of 10. A Schmitt trigger following

the CKI on-inverter ensures that the IDLE timer is clocked

only when the oscillator has a sufficiently large amplitude to

meet the Schmitt trigger specifications. This Schmitt trigger

is not part of the oscillator closed loop. The start-up time-out

from the IDLE timer enables the clock signals to be routed to

the rest of the chip.

If the RC clock option is used, the fixed delay is under soft-

ware control. A control flag, CLKDLY, in the G7 configuration

bit allows the clock start up delay to be optionally inserted.

Setting CLKDLY flag high will cause clock start up delay to

be inserted and resetting it will exclude the clock start up de-

lay. The CLKDLY flag high will cause clock start up delay.

The CLKDLY flag is cleared during reset, so the clock start

up delay is not present following reset with the RC clock op-

tions.

USART

The device contains a full-duplex software programmable

USART. The USART (

Figure 12) consists of a transmit shift

isters, as follows: a transmit buffer register (TBUF), a re-

ceiver buffer register (RBUF), a USART control and status

(ENUR), a USART interrupt and clock source register

(ENUI), a prescaler select register (PSR) and baud (BAUD)

ceive functions; this register also determines the length of

the data frame (7, 8 or 9 bits), the value of the ninth bit in

transmission, and parity selection bits. The ENUR register

flags framing, data overrun and parity errors while the US-

ART is receiving.

Other functions of the ENUR register include saving the

ninth bit received in the data frame, enabling or disabling the

USART’s attention mode of operation and providing addi-

tional receiver/transmitter status information via RCVG and

XMTG bits. The determination of an internal or external clock

source is done by the ENUI register, as well as selecting the

number of stop bits and enabling or disabling transmit and

receive interrupts. A control flag in this register can also se-

lect the USART mode of operation: asynchronous or

synchronous.

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