COP888CS datasheet(28/53 Pages) NSC

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USART Operation (Continued)

USART INTERRUPTS

The USART is capable of generating interrupts. Interrupts

are generated on Receive Buffer Full and Transmit Buffer

Empty. Both interrupts have individual interrupt vectors. Two

bytes of program memory space are reserved for each inter-

rupt vector. The two vectors are located at addresses 0xEC

to 0xEF Hex in the program memory space. The interrupts

can be individually enabled or disabled using Enable Trans-

mit Interrupt (ETI) and Enable Receive Interrupt (ERI) bits in

the ENUI register.

The interrupt from the Transmitter is set pending, and re-

mains pending, as long as both the TBMT and ETI bits are

set. To remove this interrupt, software must either clear the

ETI bit or write to the TBUF register (thus clearing the TBMT

bit).

The interrupt from the receiver is set pending, and remains

pending, as long as both the RBFL and ERI bits are set. To

remove this interrupt, software must either clear the ERI bit

or read from the RBUF register (thus clearing the RBFL bit).

Baud Clock Generation

The clock inputs to the transmitter and receiver sections of

the USART can be individually selected to come either from

an external source at the CKX pin (port L, pin L1) or from a

source selected in the PSR and BAUD registers. Internally,

the basic baud clock is created from the oscillator frequency

through a two-stage divider chain consisting of a 1–16 (in-

crements of 0.5) prescaler and an 11-bit binary counter. (

Fig-

ure 14). The divide factors are specified through two read/

write registers shown in

Figure 15. Note that the 11-bit Baud

Rate Divisor spills over into the Prescaler Select Register

(PSR). PSR is cleared upon reset.

As shown in

Table 6, a Prescaler Factor of 0 corresponds to

NO CLOCK. This condition is the USART power down mode

where the USART clock is turned off for power saving pur-

pose. The user must also turn the USART clock off when a

different baud rate is chosen.

The correspondences between the 5-bit Prescaler Select

and Prescaler factors are shown in

Table 6. There are many

ways to calculate the two divisor factors, but one particularly

effective method would be to achieve a 1.8432 MHz fre-

quency coming out of the first stage. The 1.8432 MHz pres-

caler output is then used to drive the software programmable

baud rate counter to create a 16x clock for the following baud

rates: 110, 134.5, 150, 300, 600, 1200, 1800, 2400, 3600,

4800, 7200, 9600, 19200 and 38400 (

Table 1). Other baud

rates may be created by using appropriate divisors. The 16x

clock is then divided by 16 to provide the rate for the serial

shift registers of the transmitter and receiver.

DS012829-15

FIGURE 13. Framing Formats

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