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COP8FG Datasheet(PDF) 18 Page - National Semiconductor (TI) |
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COP8FG Datasheet(HTML) 18 Page - National Semiconductor (TI) |
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18 / 59 page  5.0 Functional Description (Continued) 5.9 CONTROL REGISTERS CNTRL Register (Address X'00EE) T1C3 T1C2 T1C1 T1C0 MSEL IEDG SL1 SL0 Bit 7 Bit 0 The Timer1 (T1) and MICROWIRE/PLUS control register contains the following bits: T1C3 Timer T1 mode control bit T1C2 Timer T1 mode control bit T1C1 Timer T1 mode control bit T1C0 Timer T1 Start/Stop control in timer modes 1 and 2, T1 Underflow Interrupt Pending Flag in timer mode 3 MSEL Selects G5 and G4 as MICROWIRE/PLUS signals SK and SO respectively IEDG External interrupt edge polarity select (0 = Rising edge, 1 = Falling edge) SL1 & SL0 Select the MICROWIRE/PLUS clock divide by (00 = 2, 01 = 4, 1x = 8) PSW Register (Address X'00EF) HC C T1PNDA T1ENA EXPND BUSY EXEN GIE Bit 7 Bit 0 The PSW register contains the following select bits: HC Half Carry Flag C Carry Flag T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA in mode 1, T1 Underflow in Mode 2, T1A capture edge in mode 3) T1ENA Timer T1 Interrupt Enable for Timer Underflow or T1A Input capture edge EXPND External interrupt pending BUSY MICROWIRE/PLUS busy shifting flag EXEN Enable external interrupt GIE Global interrupt enable (enables interrupts) The Half-Carry flag is also affected by all the instructions that affect the Carry flag. The SC (Set Carry) and R/C (Reset Carry) instructions will respectively set or clear both the carry flags. In addition to the SC and R/C instructions, ADC, SUBC, RRC and RLC instructions affect the Carry and Half Carry flags. ICNTRL Register (Address X'00E8) Reserved LPEN T0PND T0EN µWPND µWEN T1PNDB T1ENB Bit 7 Bit 0 The ICNTRL register contains the following bits: Reserved This bit is reserved and must be zero LPEN L Port Interrupt Enable (Multi-Input Wakeup/ Interrupt) T0PND Timer T0 Interrupt pending T0EN Timer T0 Interrupt Enable (Bit 12 toggle) µWPND MICROWIRE/PLUS interrupt pending µWEN Enable MICROWIRE/PLUS interrupt T1PNDB Timer T1 Interrupt Pending Flag for T1B cap- ture edge T1ENB Timer T1 Interrupt Enable for T1B Input cap- ture edge T2CNTRL Register (Address X'00C6) T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB Bit 7 Bit 0 The T2CNTRL control register contains the following bits: T2C3 Timer T2 mode control bit T2C2 Timer T2 mode control bit T2C1 Timer T2 mode control bit T2C0 Timer T2 Start/Stop control in timer modes 1 and 2, T2 Underflow Interrupt Pend- ing Flag in timer mode 3 T2PNDA Timer T2 Interrupt Pending Flag (Autoreload RA in mode 1, T2 Underflow in mode 2, T2A capture edge in mode 3) T2ENA Timer T2 Interrupt Enable for Timer Underflow or T2A Input capture edge T2PNDB Timer T2 Interrupt Pending Flag for T2B cap- ture edge T2ENB Timer T2 Interrupt Enable for Timer Underflow or T2B Input capture edge T3CNTRL Register (Address X'00B6) T3C3 T3C2 T3C1 T3C0 T3PNDA T3ENA T3PNDB T3ENB Bit 7 Bit 0 The T3CNTRL control register contains the following bits: T3C3 Timer T3 mode control bit T3C2 Timer T3 mode control bit T3C1 Timer T3 mode control bit T3C0 Timer T3 Start/Stop control in timer modes 1 and 2, T3 Underflow Interrupt Pend- ing Flag in timer mode 3 T3PNDA Timer T3 Interrupt Pending Flag (Autoreload RA in mode 1, T3 Underflow in mode 2, T3A capture edge in mode 3) T3ENA Timer T3 Interrupt Enable for Timer Underflow or T3A Input capture edge T3PNDB Timer T3 Interrupt Pending Flag for T3B cap- ture edge T3ENB Timer T3 Interrupt Enable for Timer Underflow or T3B Input capture edge 6.0 Timers Each device contains a very versatile set of timers (T0, T1, T2 and T3). Timer T1, T2 and T3 and associated autoreload/ capture registers power up containing random data. 6.1 TIMER T0 (IDLE TIMER) Each device supports applications that require maintaining real time and low power with the IDLE mode. This IDLE mode support is furnished by the IDLE timer T0. The Timer T0 runs continuously at the fixed rate of the instruction cycle clock, t C. The user cannot read or write to the IDLE Timer T0, which is a count down timer. The Timer T0 supports the following functions: • Exit out of the Idle Mode (See Idle Mode description) • WATCHDOG logic (See WATCHDOG description) • Start up delay out of the HALT mode www.national.com 18 |
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